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DMAC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x12 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x13 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x7 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x11 byte (0x0)
mem_usage : registers
protection :

Registers

DMSAR

DMTMD

DMINT

DMAMD

DMOFR

DMCNT

DMREQ

DMSTS

DMSRR

DMDRR

DMSBS

DMDBS

DMBWR

DMDAR

DMCRA

DMCRB


DMSAR

DMA Source Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMSAR DMSAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMTMD

DMA Transfer Mode Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMTMD DMTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCTG SZ TKP DTS MD

DCTG : Transfer Request Source Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Software request

#01 : 01

Hardware request

#10 : 10

Setting prohibited

#11 : 11

Setting prohibited

End of enumeration elements list.

SZ : Transfer Data Size Select
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : 00

8 bits

#01 : 01

16 bits

#10 : 10

32 bits

#11 : 11

Setting prohibited

End of enumeration elements list.

TKP : Transfer Keeping
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transfer is stopped by completion of specified total number of transfer operations.

#1 : 1

Transfer is not stopped by completion of specified total number of transfer operations. (free-running)

End of enumeration elements list.

DTS : Repeat Area Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : 00

The destination is specified as the repeat area or block area

#01 : 01

The source is specified as the repeat area or block area

#10 : 10

The repeat area or block area is not specified

#11 : 11

Setting prohibited

End of enumeration elements list.

MD : Transfer Mode Select
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : 00

Normal transfer

#01 : 01

Repeat transfer

#10 : 10

Block transfer

#11 : 11

Repeat-block transfer

End of enumeration elements list.


DMINT

DMA Interrupt Setting Register
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMINT DMINT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DARIE SARIE RPTIE ESIE DTIE

DARIE : Destination Address Extended Repeat Area Overflow Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables an interrupt request for an extended repeat area overflow on the destination address

#1 : 1

Enables an interrupt request for an extended repeat area overflow on the destination address

End of enumeration elements list.

SARIE : Source Address Extended Repeat Area Overflow Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables an interrupt request for an extended repeat area overflow on the source address

#1 : 1

Enables an interrupt request for an extended repeat area overflow on the source address

End of enumeration elements list.

RPTIE : Repeat Size End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the repeat size end interrupt request

#1 : 1

Enables the repeat size end interrupt request

End of enumeration elements list.

ESIE : Transfer Escape End Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the transfer escape end interrupt request

#1 : 1

Enables the transfer escape end interrupt request

End of enumeration elements list.

DTIE : Transfer End Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the transfer end interrupt request

#1 : 1

Enables the transfer end interrupt request

End of enumeration elements list.


DMAMD

DMA Address Mode Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMD DMAMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DARA DADR DM SARA SADR SM

DARA : Destination Address Extended Repeat Area
bits : 0 - 3 (4 bit)
access : read-write

DADR : Destination Address Update Select After Reload
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Only reloading

#1 : 1

Add index after reloading

End of enumeration elements list.

DM : Destination Address Update Mode
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Destination address is fixed

#01 : 01

Offset addition

#10 : 10

Destination address is incremented

#11 : 11

Destination address is decremented

End of enumeration elements list.

SARA : Source Address Extended Repeat Area
bits : 8 - 11 (4 bit)
access : read-write

SADR : Source Address Update Select After Reload
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Only reloading

#1 : 1

Add index after reloading

End of enumeration elements list.

SM : Source Address Update Mode
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : 00

Source address is fixed

#01 : 01

Offset addition

#10 : 10

Source address is incremented

#11 : 11

Source address is decremented

End of enumeration elements list.


DMOFR

DMA Offset Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMOFR DMOFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMCNT

DMA Transfer Enable Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMCNT DMCNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTE

DTE : DMA Transfer Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables DMA transfer

#1 : 1

Enables DMA transfer

End of enumeration elements list.


DMREQ

DMA Software Start Register
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMREQ DMREQ read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWREQ CLRS

SWREQ : DMA Software Start
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMA transfer is not requested

#1 : 1

DMA transfer is requested

End of enumeration elements list.

CLRS : DMA Software Start Bit Auto Clear Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

SWREQ bit is cleared after DMA transfer is started by software

#1 : 1

SWREQ bit is not cleared after DMA transfer is started by software

End of enumeration elements list.


DMSTS

DMA Status Register
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMSTS DMSTS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ESIF DTIF ACT

ESIF : Transfer Escape End Interrupt Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A transfer escape end interrupt has not been generated

#1 : 1

A transfer escape end interrupt has been generated

End of enumeration elements list.

DTIF : Transfer End Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

A transfer end interrupt has not been generated

#1 : 1

A transfer end interrupt has been generated

End of enumeration elements list.

ACT : DMAC Active Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

DMAC is in the idle state

#1 : 1

DMAC is operating

End of enumeration elements list.


DMSRR

DMA Source Reload Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMSRR DMSRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMDRR

DMA Destination Reload Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMDRR DMDRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMSBS

DMA Source Buffer Size Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMSBS DMSBS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMSBSL DMSBSH

DMSBSL : Functions as data transfer counter in repeat-block transfer mode
bits : 0 - 14 (15 bit)
access : read-write

DMSBSH : Specifies the repeat-area size in repeat-block transfer mode
bits : 16 - 30 (15 bit)
access : read-write


DMDBS

DMA Destination Buffer Size Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMDBS DMDBS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMDBSL DMDBSH

DMDBSL : Functions as data transfer counter in repeat-block transfer mode
bits : 0 - 14 (15 bit)
access : read-write

DMDBSH : Specifies the repeat-area size in repeat-block transfer mode
bits : 16 - 30 (15 bit)
access : read-write


DMBWR

DMA Bufferable Write Enable Register
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMBWR DMBWR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BWE

BWE : Bufferable Write Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables Bufferable Write

#1 : 1

Enables Bufferable Write

End of enumeration elements list.


DMDAR

DMA Destination Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMDAR DMDAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMCRA

DMA Transfer Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMCRA DMCRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMCRAL DMCRAH

DMCRAL : Lower bits of transfer count
bits : 0 - 14 (15 bit)
access : read-write

DMCRAH : Upper bits of transfer count
bits : 16 - 24 (9 bit)
access : read-write


DMCRB

DMA Block Transfer Count Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMCRB DMCRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMCRBL DMCRBH

DMCRBL : Functions as a number of block, repeat or repeat-block transfer counter.
bits : 0 - 14 (15 bit)
access : read-write

DMCRBH : Specifies the number of block, repeat or repeat-block transfer operations.
bits : 16 - 30 (15 bit)
access : read-write



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