\n

AGT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

AGT

AGTCMA

AGTCMB

AGTCR

AGTMR1

AGTMR2

AGTIOC

AGTISR

AGTCMSR

AGTIOSEL


AGT

AGT Counter Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGT AGT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGT

AGT : 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH.
bits : 0 - 14 (15 bit)
access : read-write


AGTCMA

AGT Compare Match A Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTCMA AGTCMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGTCMA

AGTCMA : AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH
bits : 0 - 14 (15 bit)
access : read-write


AGTCMB

AGT Compare Match B Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTCMB AGTCMB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGTCMB

AGTCMB : AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH
bits : 0 - 14 (15 bit)
access : read-write


AGTCR

AGT Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTCR AGTCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TSTART TCSTF TSTOP Reserved TEDGF TUNDF TCMAF TCMBF

TSTART : AGT count start
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Count stops

#1 : 1

Count starts

End of enumeration elements list.

TCSTF : AGT count status flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Count stops

#1 : 1

Count starts

End of enumeration elements list.

TSTOP : AGT count forced stop
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : 0

no effect

#1 : 1

The count is forcibly stopped.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write

TEDGF : Active edge judgement flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No active edge received

#1 : 1

Active edge received

End of enumeration elements list.

TUNDF : AGT underflow flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

No underflow

#1 : 1

Underflow

End of enumeration elements list.

TCMAF : AGT compare match A flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No Match

#1 : 1

Match

End of enumeration elements list.

TCMBF : AGT compare match B flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

No Match

#1 : 1

Match

End of enumeration elements list.


AGTMR1

AGT Mode Register 1
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTMR1 AGTMR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TMOD TEDGPL TCK Reserved

TMOD : AGT operating mode select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

Timer mode

#001 : 001

Pulse output mode

#010 : 010

Event counter mode

#011 : 011

Pulse width measurement mode

#100 : 100

Pulse period measurement mode

: others

Setting prohibited

End of enumeration elements list.

TEDGPL : AGTIO edge polarity select
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

One edge

#1 : 1

Both edges

End of enumeration elements list.

TCK : AGT count source select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

PCLKB

#001 : 001

PCLKB/8

#011 : 011

PCLKB/2

#100 : 100

Divided clock LOCO specified by AGTMR2.CKS bit.

#101 : 101

Underflow event signal from AGT

#110 : 110

Divided clock fSUB specified by AGTMR2.CKS bit.

: others

Setting prohibited

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write


AGTMR2

AGT Mode Register 2
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTMR2 AGTMR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS Reserved LPM

CKS : fsub/LOCO count source clock frequency division ratio select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

1/1

#001 : 001

1/2

#010 : 010

1/4

#011 : 011

1/8

#100 : 100

1/16

#101 : 101

1/32

#110 : 110

1/64

#111 : 111

1/128

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 3 - 5 (3 bit)
access : read-write

LPM : AGT Low Power Mode
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Low Power mode

End of enumeration elements list.


AGTIOC

AGT I/O Control Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTIOC AGTIOC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TEDGSEL TOE Reserved Reserved TIPF TIOGT

TEDGSEL : I/O polarity switchFunction varies depending on the operating mode.
bits : 0 - -1 (0 bit)
access : read-write

TOE : AGTO output enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

AGTO output disabled (port)

#1 : 1

AGTO output enabled

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write

TIPF : AGTIO input filter select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

No filter

#01 : 01

Filter sampled at PCLKB

#10 : 10

Filter sampled at PCLKB/8

#11 : 11

Filter sampled at PCLKB/32

End of enumeration elements list.

TIOGT : AGTIO count control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Event is always counted

#01 : 01

Event is counted during polarity period specified for AGTEE

: others

Setting prohibited

End of enumeration elements list.


AGTISR

AGT Event Pin Select Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTISR AGTISR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EEPS Reserved Reserved

EEPS : AGTEE polarty selection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

An event is counted during the low-level period

#1 : 1

An event is counted during the high-level period

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write


AGTCMSR

AGT Compare Match Function Select Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTCMSR AGTCMSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TCMEA TOEA TOPOLA TCMEB TOEB TOPOLB Reserved Reserved

TCMEA : Compare match A register enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable compare match A register

#1 : 1

Enable compare match A register

End of enumeration elements list.

TOEA : AGTOA output enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

AGTOA output disabled (port)

#1 : 1

AGTOA output enabled

End of enumeration elements list.

TOPOLA : AGTOA polarity select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

AGTOA Output is started at low

#1 : 1

AGTOA Output is started at high

End of enumeration elements list.

TCMEB : Compare match B register enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable compare match B register

#1 : 1

Enable compare match B register

End of enumeration elements list.

TOEB : AGTOB output enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

AGTOB output disabled (port)

#1 : 1

AGTOB output enabled

End of enumeration elements list.

TOPOLB : AGTOB polarity select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

AGTOB Output is started at low

#1 : 1

AGTOB Output is started at high

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write


AGTIOSEL

AGT Pin Select Register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGTIOSEL AGTIOSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEL TIES Reserved Reserved

SEL : AGTIO pin select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

AGTIO_A can not be used as AGTIO input pin in deep software standby mode

#01 : 01

Setting prohibited

#10 : 10

AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output.

#11 : 11

AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output.

End of enumeration elements list.

TIES : AGTIO input enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

external event input disable during software standby mode

#1 : 1

external event input enable during software standby mode

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.