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EDMAC Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software Reset
bits : 0 - -1 (0 bit)
access : read-write
DL : Transmit/Receive Descriptor Length
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
16 bytes
#01 : 01
32 bytes
#10 : 10
64 bytes
#11 : 11
16 bytes.
End of enumeration elements list.
DE : Big Endian Mode/Little Endian Mode
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Big endian mode
#1 : 1
Little endian mode.
End of enumeration elements list.
EDMAC Receive Request Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RR : Receive Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the receive function
#1 : 1
Read receive descriptor and enable the receive function.
End of enumeration elements list.
Transmit Descriptor List Start Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive Descriptor List Start Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETHERC/EDMAC Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CERF : CRC Error Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
CRC error not detected
#1 : 1
CRC error detected.
End of enumeration elements list.
PRE : PHY-LSI Receive Error Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
PHY-LSI receive error not detected
#1 : 1
PHY-LSI receive error detected.
End of enumeration elements list.
RTSF : Frame-Too-Short Error Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame-too-short error not detected
#1 : 1
Frame-too-short error detected.
End of enumeration elements list.
RTLF : Frame-Too-Long Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame-too-long error not detected
#1 : 1
Frame-too-long error detected.
End of enumeration elements list.
RRF : Alignment Error Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Alignment error not detected
#1 : 1
Alignment error detected.
End of enumeration elements list.
RMAF : Multicast Address Frame Receive Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Multicast address frame not received
#1 : 1
Multicast address frame received.
End of enumeration elements list.
TRO : Transmit Retry Over Flag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit retry-over condition not detected
#1 : 1
Transmit retry-over condition detected.
End of enumeration elements list.
CD : Late Collision Detect Flag
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Late collision not detected
#1 : 1
Late collision detected during frame transmission.
End of enumeration elements list.
DLC : Loss of Carrier Detect Flag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Loss of carrier not detected
#1 : 1
Loss of carrier detected during frame transmission.
End of enumeration elements list.
CND : Carrier Not Detect Flag
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Carrier detected when transmission started
#1 : 1
Carrier not detected during preamble transmission.
End of enumeration elements list.
RFOF : Receive FIFO Overflow Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overflow occurred
#1 : 1
Overflow occurred.
End of enumeration elements list.
RDE : Receive Descriptor Empty Flag
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
EDMAC detected that the receive descriptor valid bit (RD0.RACT) is 1
#1 : 1
EDMAC detected that the receive descriptor valid bit (RD0.RACT) is 0.
End of enumeration elements list.
FR : Frame Receive Flag
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame not received
#1 : 1
Frame received and update of the receive descriptor is complete.
End of enumeration elements list.
TFUF : Transmit FIFO Underflow Flag
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
No underflow occurred
#1 : 1
Underflow occurred.
End of enumeration elements list.
TDE : Transmit Descriptor Empty Flag
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
EDMAC detected that the transmit descriptor valid bit (TD0.TACT) is 1
#1 : 1
EDMAC detected that the transmit descriptor valid bit (TD0.TACT) is 0.
End of enumeration elements list.
TC : Frame Transfer Complete Flag
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transfer not complete or no transfer requested
#1 : 1
All frames indicated in the transmit descriptor were completely transferred to the transmit FIFO.
End of enumeration elements list.
ECI : ETHERC Status Register Source Flag
bits : 22 - 21 (0 bit)
access : read-only
Enumeration:
#0 : 0
ETHERC status interrupt source not detected
#1 : 1
ETHERC status interrupt source detected.
End of enumeration elements list.
ADE : Address Error Flag
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid memory address not detected (normal operation)
#1 : 1
Invalid memory address detected.
End of enumeration elements list.
RFCOF : Receive Frame Counter Overflow Flag
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame counter did not overflow
#1 : 1
Receive frame counter overflowed.
End of enumeration elements list.
RABT : Receive Abort Detect Flag
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame reception not aborted or no reception requested
#1 : 1
Frame reception aborted.
End of enumeration elements list.
TABT : Transmit Abort Detect Flag
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame transmission not aborted or no transmission requested.
#1 : 1
Frame transmission aborted.
End of enumeration elements list.
TWB : Write-Back Complete Flag
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write-back not complete or no transmission requested
#1 : 1
Write-back to the transmit descriptor completed.
End of enumeration elements list.
ETHERC/EDMAC Status Interrupt Enable Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CERFIP : CRC Error Interrupt Request Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable CRC error interrupt requests
#1 : 1
Enable CRC error interrupt requests.
End of enumeration elements list.
PREIP : PHY-LSI Receive Error Interrupt Request Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable PHY-LSI receive error interrupt requests
#1 : 1
Enable PHY-LSI receive error interrupt requests.
End of enumeration elements list.
RTSFIP : Frame-Too-Short Error Interrupt Request Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable frame-too-short error interrupt requests
#1 : 1
Enable frame-too-short error interrupt requests.
End of enumeration elements list.
RTLFIP : Frame-Too-Long Error Interrupt Request Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable frame-too-long error interrupt requests
#1 : 1
Enable frame-too-long error interrupt requests.
End of enumeration elements list.
RRFIP : Alignment Error Interrupt Request Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable alignment error interrupt requests
#1 : 1
Enable alignment error interrupt requests.
End of enumeration elements list.
RMAFIP : Multicast Address Frame Receive Interrupt Request Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable multicast address frame receive interrupt requests
#1 : 1
Enable multicast address frame receive interrupt requests.
End of enumeration elements list.
TROIP : Transmit Retry Over Interrupt Request Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transmit retry over interrupt requests
#1 : 1
Enable transmit retry over interrupt requests.
End of enumeration elements list.
CDIP : Late Collision Detect Interrupt Request Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable late collision detected interrupt requests
#1 : 1
Enable late collision detected interrupt requests.
End of enumeration elements list.
DLCIP : Loss of Carrier Detect Interrupt Request Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable loss of carrier detected interrupt requests
#1 : 1
Enable loss of carrier detected interrupt requests.
End of enumeration elements list.
CNDIP : Carrier Not Detect Interrupt Request Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable carrier not detected interrupt requests
#1 : 1
Enable carrier not detected interrupt requests.
End of enumeration elements list.
RFOFIP : Receive FIFO Overflow Interrupt Request Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable overflow interrupt requests
#1 : 1
Enable overflow interrupt requests.
End of enumeration elements list.
RDEIP : Receive Descriptor Empty Interrupt Request Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable receive descriptor empty interrupt requests
#1 : 1
Enable receive descriptor empty interrupt requests.
End of enumeration elements list.
FRIP : Frame Receive Interrupt Request Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable frame reception interrupt requests
#1 : 1
Enable frame reception interrupt requests.
End of enumeration elements list.
TFUFIP : Transmit FIFO Underflow Interrupt Request Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable underflow interrupt requests
#1 : 1
Enable underflow interrupt requests.
End of enumeration elements list.
TDEIP : Transmit Descriptor Empty Interrupt Request Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transmit descriptor empty interrupt requests
#1 : 1
Enable transmit descriptor empty interrupt requests.
End of enumeration elements list.
TCIP : Frame Transfer Complete Interrupt Request Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable frame transmission complete interrupt requests
#1 : 1
Enable frame transmission complete interrupt requests.
End of enumeration elements list.
ECIIP : ETHERC Status Register Source Interrupt Request Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable ETHERC status interrupt requests
#1 : 1
Enable ETHERC status interrupt requests.
End of enumeration elements list.
ADEIP : Address Error Interrupt Request Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable address error interrupt requests
#1 : 1
Enable address error interrupt requests.
End of enumeration elements list.
RFCOFIP : Receive Frame Counter Overflow Interrupt Request Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable receive frame counter overflow interrupt requests
#1 : 1
Enable receive frame counter overflow interrupt requests.
End of enumeration elements list.
RABTIP : Receive Abort Detect Interrupt Request Enable
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable receive abort detected interrupt requests
#1 : 1
Enable receive abort detected interrupt requests.
End of enumeration elements list.
TABTIP : Transmit Abort Detect Interrupt Request Enable
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transmit abort detected interrupt requests
#1 : 1
Enable transmit abort detected interrupt requests.
End of enumeration elements list.
TWBIP : Write-Back Complete Interrupt Request Enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable write-back complete interrupt requests
#1 : 1
Enable write-back complete interrupt requests.
End of enumeration elements list.
ETHERC/EDMAC Transmit/Receive Status Copy Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFCE : RRF Flag Copy Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reflect the EESR.RRF flag status in the RD0.RFE bit of the receive descriptor
#1 : 1
Do not reflect the EESR.RRF flag status in the RD0.RFE bit of the receive descriptor.
End of enumeration elements list.
RMAFCE : RMAF Flag Copy Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reflect the EESR.RMAF flag status in the RD0.RFE bit of the receive descriptor
#1 : 1
Do not reflect the EESR.RMAF flag status in the RD0.RFE bit of the receive descriptor.
End of enumeration elements list.
Missed-Frame Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFC : Missed-Frame Counter
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Threshold Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFT : Transmit FIFO Threshold
bits : 0 - 9 (10 bit)
access : read-write
Enumeration:
0x000 : 0x000
Store-and-forward mode
0x01 : 0x01
Setting prohibited
0x02 : 0x02
Setting prohibited
0x03 : 0x03
Setting prohibited
0x04 : 0x04
Setting prohibited
0x05 : 0x05
Setting prohibited
0x06 : 0x06
Setting prohibited
0x07 : 0x07
Setting prohibited
0x08 : 0x08
Setting prohibited
0x09 : 0x09
Setting prohibited
0x10 : 0x0a
Setting prohibited
0x11 : 0x0b
Setting prohibited
0x12 : 0x0c
Setting prohibited
: Other
The threshold is the set value multiplied by 4.
End of enumeration elements list.
FIFO Depth Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD : Receive FIFO Depth
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0f : 0x0F
4096 bytes.
: Others
settings prohibited.
End of enumeration elements list.
TFD : Transmit FIFO Depth
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0x07 : 0x07
2048 bytes.
: Others
settings prohibited.
End of enumeration elements list.
Receive Method Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNR : Receive Request Reset
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
EDRRR.RR bit (receive request bit) is cleared to 0 when one frame is received
#1 : 1
EDRRR.RR bit (receive request bit) is not cleared to 0 when one frame is received.
End of enumeration elements list.
Transmit FIFO Underflow Counter
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNDER : Transmit FIFO Underflow Count
bits : 0 - 14 (15 bit)
access : read-write
Receive FIFO Overflow Counter
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVER : Receive FIFO Overflow Count
bits : 0 - 14 (15 bit)
access : read-write
Independent Output Signal Setting Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELB : External Loopback Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output low on the ET0_EXOUT pin
#1 : 1
Output high on the ET0_EXOUT pin.
End of enumeration elements list.
Flow Control Start FIFO Threshold Setting Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFDO : Receive FIFO Data PAUSE Output Threshold
bits : 0 - 1 (2 bit)
access : read-write
RFFO : Receive FIFO Frame PAUSE Output Threshold
bits : 16 - 17 (2 bit)
access : read-write
Receive Data Padding Insert Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADR : Padding Slot
bits : 0 - 4 (5 bit)
access : read-write
PADS : Padding Size
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not insert padding
: Others
settings prohibited
End of enumeration elements list.
Transmit Interrupt Setting Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIS : Transmit Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transmit interrupts
#1 : 1
Enable transmit Interrupts.
End of enumeration elements list.
TIM : Transmit Interrupt Mode
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Select transmission complete interrupt mode, where an interrupt occurs when a frame is transmitted
#1 : 1
Select write-back complete interrupt mode, where an interrupt occurs when write-back to the transmit descriptor is complete while the TWBI bit is 1.
End of enumeration elements list.
EDMAC Transmit Request Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR : Transmit Request
bits : 0 - -1 (0 bit)
access : read-write
Receive Buffer Write Address Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Receive Descriptor Fetch Address Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Transmit Buffer Read Address Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Transmit Descriptor Fetch Address Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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