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ETHERC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x50 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x60 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x6C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xE4 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

ECMR

ECSR

ECSIPR

PIR

PSR

RDMLR

IPGR

APR

MPR

RFCF

TPAUSECR

TPAUSER

BCFRR

RFLR

MAHR

MALR

TROCR

CDCR

LCCR

CNDCR

CEFCR

FRECR

TSFRCR

TLFRCR

RFCR

MAFCR


ECMR

ETHERC Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECMR ECMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRM DM RTM ILB TE RE MPDE PRCEF TXF RXF PFR ZPF TPC

PRM : Promiscuous Mode
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable promiscuous mode

#1 : 1

Enable promiscuous mode.

End of enumeration elements list.

DM : Duplex Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Half-duplex mode

#1 : 1

Full-duplex mode.

End of enumeration elements list.

RTM : Bit Rate
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

10 Mbps

#1 : 1

100 Mbps.

End of enumeration elements list.

ILB : Internal Loopback Mode
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Perform normal data transmission or reception

#1 : 1

Loop data back in the ETHERC when full-duplex mode is selected.

End of enumeration elements list.

TE : Transmission Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable transmit function

#1 : 1

Enable transmit function.

End of enumeration elements list.

RE : Reception Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable receive function

#1 : 1

Enable receive function.

End of enumeration elements list.

MPDE : Magic Packet Detection Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable Magic Packet detection

#1 : 1

Enable Magic Packet detection.

End of enumeration elements list.

PRCEF : CRC Error Frame Receive Mode
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Notify EDMAC of a CRC error

#1 : 1

Do not notify EDMAC of a CRC error.

End of enumeration elements list.

TXF : Transmit Flow Control Operating Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable automatic PAUSE frame transmission (PAUSE frame is not automatically transmitted)

#1 : 1

Enable automatic PAUSE frame transmission (PAUSE frame is automatically transmitted as required).

End of enumeration elements list.

RXF : Receive Flow Control Operating Mode
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable PAUSE frame detection

#1 : 1

Enable PAUSE frame detection.

End of enumeration elements list.

PFR : PAUSE Frame Receive Mode
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not transfer PAUSE frame to the EDMAC

#1 : 1

Transfer PAUSE frame to the EDMAC.

End of enumeration elements list.

ZPF : 0 Time PAUSE Frame Enable
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not use PAUSE frames that containing a pause_time parameter of 0

#1 : 1

Use PAUSE frames that containing a pause_time parameter of 0.

End of enumeration elements list.

TPC : PAUSE Frame Transmit
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmit PAUSE frame even during a PAUSE period

#1 : 1

Do not transmit PAUSE frame during a PAUSE period.

End of enumeration elements list.


ECSR

ETHERC Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECSR ECSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICD MPD LCHNG PSRTO BFR

ICD : False Carrier Detect Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

PHY-LSI has not detected a false carrier on the line

#1 : 1

PHY-LSI detected a false carrier on the line.

End of enumeration elements list.

MPD : Magic Packet Detect Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Magic Packet not detected

#1 : 1

Magic Packet detected.

End of enumeration elements list.

LCHNG : Link Signal Change Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Change in the ET0_LINKSTA signal not detected

#1 : 1

Change in the ET0_LINKSTA signal detected (high to low, or low to high).

End of enumeration elements list.

PSRTO : PAUSE Frame Retransmit Over Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

PAUSE frame retransmit count has not reached the upper limit

#1 : 1

PAUSE frame retransmit count reached the upper limit.

End of enumeration elements list.

BFR : Continuous Broadcast Frame Reception Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Continuous reception of broadcast frames not detected

#1 : 1

Continuous reception of broadcast frames detected.

End of enumeration elements list.


ECSIPR

ETHERC Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECSIPR ECSIPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICDIP MPDIP LCHNGIP PSRTOIP BFSIPR

ICDIP : False Carrier Detect Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt notification

#1 : 1

Enable interrupt notification.

End of enumeration elements list.

MPDIP : Magic Packet Detect Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt notification

#1 : 1

Enable interrupt notification.

End of enumeration elements list.

LCHNGIP : LINK Signal Change Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt notification

#1 : 1

Enable interrupt notification.

End of enumeration elements list.

PSRTOIP : PAUSE Frame Retransmit Over Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt notification

#1 : 1

Enable interrupt notification.

End of enumeration elements list.

BFSIPR : Continuous Broadcast Frame Reception Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt notification

#1 : 1

Enable interrupt notification.

End of enumeration elements list.


PIR

PHY Interface Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIR PIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDC MMD MDO MDI

MDC : MII/RMII Management Data Clock
bits : 0 - -1 (0 bit)
access : read-write

MMD : MII/RMII Management Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read

#1 : 1

Write.

End of enumeration elements list.

MDO : MII/RMII Management Data-Out
bits : 2 - 1 (0 bit)
access : read-write

MDI : MII/RMII Management Data-In
bits : 3 - 2 (0 bit)
access : read-only


PSR

PHY Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSR PSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMON

LMON : ET0_LINKSTA Pin Status Flag
bits : 0 - -1 (0 bit)
access : read-only


RDMLR

Random Number Generation Counter Upper Limit Setting Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDMLR RDMLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMD

RMD : Random Number Generation Counter
bits : 0 - 18 (19 bit)
access : read-write


IPGR

Interpacket Gap Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPGR IPGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPG

IPG :
bits : 0 - 3 (4 bit)
access : read-write


APR

Automatic PAUSE Frame Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APR APR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AP

AP : Automatic PAUSE Time Setting
bits : 0 - 14 (15 bit)
access : read-write


MPR

Manual PAUSE Frame Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPR MPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MP

MP : Manual PAUSE Time Setting
bits : 0 - 14 (15 bit)
access : read-write


RFCF

Received PAUSE Frame Counter
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RFCF RFCF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPAUSE

RPAUSE : Received PAUSE Frame Count
bits : 0 - 6 (7 bit)
access : read-only


TPAUSECR

PAUSE Frame Retransmit Counter
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : RFCF
reset_Mask : 0x0

TPAUSECR TPAUSECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXP

TXP : PAUSE Frame Retransmit Count
bits : 0 - 6 (7 bit)
access : read-only


TPAUSER

PAUSE Frame Retransmit Count Setting Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPAUSER TPAUSER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPAUSE

TPAUSE :
bits : 0 - 14 (15 bit)
access : read-write


BCFRR

Broadcast Frame Receive Count Setting Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCFRR BCFRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCF

BCF :
bits : 0 - 14 (15 bit)
access : read-write


RFLR

Receive Frame Maximum Length Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFLR RFLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFL

RFL : Receive Frame Maximum Length
bits : 0 - 10 (11 bit)
access : read-write


MAHR

MAC Address Upper Bit Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAHR MAHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAHR

MAHR : MAC Address Upper Bit
bits : 0 - 30 (31 bit)
access : read-write


MALR

MAC Address Lower Bit Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MALR MALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MALR

MALR : MAC Address Lower Bit
bits : 0 - 14 (15 bit)
access : read-write


TROCR

Transmit Retry Over Counter Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TROCR TROCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TROCR

TROCR : Transmit Retry Over Counter
bits : 0 - 30 (31 bit)
access : read-write


CDCR

Late Collision Detect Counter Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDCR CDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDCR

CDCR : Late Collision Detect Counter
bits : 0 - 30 (31 bit)
access : read-write


LCCR

Lost Carrier Counter Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCCR LCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCCR

LCCR : Lost Carrier Counter
bits : 0 - 30 (31 bit)
access : read-write


CNDCR

Carrier Not Detect Counter Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDCR CNDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNDCR

CNDCR : Carrier Not Detect Counter
bits : 0 - 30 (31 bit)
access : read-write


CEFCR

CRC Error Frame Receive Counter Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEFCR CEFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEFCR

CEFCR : CRC Error Frame Receive Counter
bits : 0 - 30 (31 bit)
access : read-write


FRECR

Frame Receive Error Counter Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRECR FRECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRECR

FRECR : Frame Receive Error Counter
bits : 0 - 30 (31 bit)
access : read-write


TSFRCR

Too-Short Frame Receive Counter Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSFRCR TSFRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSFRCR

TSFRCR : Too-Short Frame Receive Counter
bits : 0 - 30 (31 bit)
access : read-write


TLFRCR

Too-Long Frame Receive Counter Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TLFRCR TLFRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLFRCR

TLFRCR : Too-Long Frame Receive Counter
bits : 0 - 30 (31 bit)
access : read-write


RFCR

Received Alignment Error Frame Counter Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFCR RFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCR

RFCR : Received Alignment Error Frame Counter
bits : 0 - 30 (31 bit)
access : read-write


MAFCR

Multicast Address Frame Receive Counter Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAFCR MAFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAFCR

MAFCR : Multicast Address Frame Receive Counter
bits : 0 - 30 (31 bit)
access : read-write



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