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SPI0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x1A byte (0x0)
mem_usage : registers
protection :

address_offset : 0x3E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

Registers

SPCR

SSLP

SPCMD0

SPCMD1

SPCMD2

SPCMD3

SPCMD4

SPCMD5

SPCMD6

SPCMD7

SPPCR

SPDCR2

SPCR3

SPSR

SPPR

SPDR

SPDR_HA

SPSCR

SPSSR

SPBR

SPDCR

SPCKD

SSLND

SPND

SPCR2


SPCR

SPI Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCR SPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPMS TXMD MODFEN MSTR SPEIE SPTIE SPE SPRIE

SPMS : SPI Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

SPI operation (4-wire method)

#1 : 1

Clock synchronous operation (3-wire method)

End of enumeration elements list.

TXMD : Communications Operating Mode Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Full-duplex synchronous serial communications

#1 : 1

Serial communications consisting of only transmit operations

End of enumeration elements list.

MODFEN : Mode Fault Error Detection Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the detection of mode fault error

#1 : 1

Enables the detection of mode fault error

End of enumeration elements list.

MSTR : SPI Master/Slave Mode Select
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Slave mode

#1 : 1

Master mode

End of enumeration elements list.

SPEIE : SPI Error Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the generation of SPI error interrupt requests

#1 : 1

Enables the generation of SPI error interrupt requests

End of enumeration elements list.

SPTIE : Transmit Buffer Empty Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the generation of transmit buffer empty interrupt requests

#1 : 1

Enables the generation of transmit buffer empty interrupt requests

End of enumeration elements list.

SPE : SPI Function Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the SPI function

#1 : 1

Enables the SPI function

End of enumeration elements list.

SPRIE : SPI Receive Buffer Full Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the generation of SPI receive buffer full interrupt requests

#1 : 1

Enables the generation of SPI receive buffer full interrupt requests

End of enumeration elements list.


SSLP

SPI Slave Select Polarity Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSLP SSLP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SSL0P SSL1P SSL2P SSL3P SSL4P SSL5P SSL6P SSL7P

SSL0P : SSL0 Signal Polarity Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

SSL0 signal is active low

#1 : 1

SSL0 signal is active high

End of enumeration elements list.

SSL1P : SSL1 Signal Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

SSL1 signal is active low

#1 : 1

SSL1 signal is active high

End of enumeration elements list.

SSL2P : SSL2 Signal Polarity Setting
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

SSL2 signal is active low

#1 : 1

SSL2 signal is active high

End of enumeration elements list.

SSL3P : SSL3 Signal Polarity Setting
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

SSL3 signal is active low

#1 : 1

SSL3 signal is active high

End of enumeration elements list.

SSL4P : SSL4 Signal Polarity Setting
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

SSL4 signal is active low

#1 : 1

SSL4 signal is active high

End of enumeration elements list.

SSL5P : SSL5 Signal Polarity Setting
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

SSL5 signal is active low

#1 : 1

SSL5 signal is active high

End of enumeration elements list.

SSL6P : SSL6 Signal Polarity Setting
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

SSL6 signal is active low

#1 : 1

SSL6 signal is active high

End of enumeration elements list.

SSL7P : SSL7 Signal Polarity Setting
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

SSL7 signal is active low

#1 : 1

SSL7 signal is active high

End of enumeration elements list.


SPCMD0

SPI Command Register %s
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD0 SPCMD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SSLKP SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data sampling on odd edge, data variation on even edge

#1 : 1

Data variation on odd edge, data sampling on even edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

RSPCK is low when idle

#1 : 1

RSPCK is high when idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

These bits select the base bit rate

#01 : 01

These bits select the base bit rate divided by 2

#10 : 10

These bits select the base bit rate divided by 4

#11 : 11

These bits select the base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

#100 : 100

SSL4

#101 : 101

SSL5

#110 : 110

SSL6

#111 : 111

SSL7

End of enumeration elements list.

SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate all SSL signals on completion of transfer

#1 : 1

Keep SSL signal level from the end of transfer until the beginning of the next access.

End of enumeration elements list.

SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

20 bits

#0001 : 0001

24 bits

#0010 : 0010

32 bits

#0011 : 0011

32 bits

#1000 : 1000

9 bits

#1001 : 1001

10 bits

#1010 : 1010

11 bits

#1011 : 1011

12 bits

#1100 : 1100

13 bits

#1101 : 1101

14 bits

#1110 : 1110

15 bits

#1111 : 1111

16 bits

: others

8bits

End of enumeration elements list.

LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB first

#1 : 1

LSB first

End of enumeration elements list.

SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

A next-access delay of 1 RSPCK + 2 PCLK

#1 : 1

A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

An SSL negation delay of 1 RSPCK

#1 : 1

An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

An RSPCK delay of 1 RSPCK

#1 : 1

An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

End of enumeration elements list.


SPCMD1

SPI Command Register %s
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD1 SPCMD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SSLKP SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data sampling on odd edge, data variation on even edge

#1 : 1

Data variation on odd edge, data sampling on even edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

RSPCK is low when idle

#1 : 1

RSPCK is high when idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

These bits select the base bit rate

#01 : 01

These bits select the base bit rate divided by 2

#10 : 10

These bits select the base bit rate divided by 4

#11 : 11

These bits select the base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

#100 : 100

SSL4

#101 : 101

SSL5

#110 : 110

SSL6

#111 : 111

SSL7

End of enumeration elements list.

SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate all SSL signals on completion of transfer

#1 : 1

Keep SSL signal level from the end of transfer until the beginning of the next access.

End of enumeration elements list.

SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

20 bits

#0001 : 0001

24 bits

#0010 : 0010

32 bits

#0011 : 0011

32 bits

#1000 : 1000

9 bits

#1001 : 1001

10 bits

#1010 : 1010

11 bits

#1011 : 1011

12 bits

#1100 : 1100

13 bits

#1101 : 1101

14 bits

#1110 : 1110

15 bits

#1111 : 1111

16 bits

: others

8bits

End of enumeration elements list.

LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB first

#1 : 1

LSB first

End of enumeration elements list.

SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

A next-access delay of 1 RSPCK + 2 PCLK

#1 : 1

A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

An SSL negation delay of 1 RSPCK

#1 : 1

An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

An RSPCK delay of 1 RSPCK

#1 : 1

An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

End of enumeration elements list.


SPCMD2

SPI Command Register %s
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD2 SPCMD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SSLKP SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data sampling on odd edge, data variation on even edge

#1 : 1

Data variation on odd edge, data sampling on even edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

RSPCK is low when idle

#1 : 1

RSPCK is high when idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

These bits select the base bit rate

#01 : 01

These bits select the base bit rate divided by 2

#10 : 10

These bits select the base bit rate divided by 4

#11 : 11

These bits select the base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

#100 : 100

SSL4

#101 : 101

SSL5

#110 : 110

SSL6

#111 : 111

SSL7

End of enumeration elements list.

SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate all SSL signals on completion of transfer

#1 : 1

Keep SSL signal level from the end of transfer until the beginning of the next access.

End of enumeration elements list.

SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

20 bits

#0001 : 0001

24 bits

#0010 : 0010

32 bits

#0011 : 0011

32 bits

#1000 : 1000

9 bits

#1001 : 1001

10 bits

#1010 : 1010

11 bits

#1011 : 1011

12 bits

#1100 : 1100

13 bits

#1101 : 1101

14 bits

#1110 : 1110

15 bits

#1111 : 1111

16 bits

: others

8bits

End of enumeration elements list.

LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB first

#1 : 1

LSB first

End of enumeration elements list.

SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

A next-access delay of 1 RSPCK + 2 PCLK

#1 : 1

A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

An SSL negation delay of 1 RSPCK

#1 : 1

An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

An RSPCK delay of 1 RSPCK

#1 : 1

An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

End of enumeration elements list.


SPCMD3

SPI Command Register %s
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD3 SPCMD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SSLKP SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data sampling on odd edge, data variation on even edge

#1 : 1

Data variation on odd edge, data sampling on even edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

RSPCK is low when idle

#1 : 1

RSPCK is high when idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

These bits select the base bit rate

#01 : 01

These bits select the base bit rate divided by 2

#10 : 10

These bits select the base bit rate divided by 4

#11 : 11

These bits select the base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

#100 : 100

SSL4

#101 : 101

SSL5

#110 : 110

SSL6

#111 : 111

SSL7

End of enumeration elements list.

SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate all SSL signals on completion of transfer

#1 : 1

Keep SSL signal level from the end of transfer until the beginning of the next access.

End of enumeration elements list.

SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

20 bits

#0001 : 0001

24 bits

#0010 : 0010

32 bits

#0011 : 0011

32 bits

#1000 : 1000

9 bits

#1001 : 1001

10 bits

#1010 : 1010

11 bits

#1011 : 1011

12 bits

#1100 : 1100

13 bits

#1101 : 1101

14 bits

#1110 : 1110

15 bits

#1111 : 1111

16 bits

: others

8bits

End of enumeration elements list.

LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB first

#1 : 1

LSB first

End of enumeration elements list.

SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

A next-access delay of 1 RSPCK + 2 PCLK

#1 : 1

A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

An SSL negation delay of 1 RSPCK

#1 : 1

An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

An RSPCK delay of 1 RSPCK

#1 : 1

An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

End of enumeration elements list.


SPCMD4

SPI Command Register %s
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD4 SPCMD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SSLKP SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data sampling on odd edge, data variation on even edge

#1 : 1

Data variation on odd edge, data sampling on even edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

RSPCK is low when idle

#1 : 1

RSPCK is high when idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

These bits select the base bit rate

#01 : 01

These bits select the base bit rate divided by 2

#10 : 10

These bits select the base bit rate divided by 4

#11 : 11

These bits select the base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

#100 : 100

SSL4

#101 : 101

SSL5

#110 : 110

SSL6

#111 : 111

SSL7

End of enumeration elements list.

SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate all SSL signals on completion of transfer

#1 : 1

Keep SSL signal level from the end of transfer until the beginning of the next access.

End of enumeration elements list.

SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

20 bits

#0001 : 0001

24 bits

#0010 : 0010

32 bits

#0011 : 0011

32 bits

#1000 : 1000

9 bits

#1001 : 1001

10 bits

#1010 : 1010

11 bits

#1011 : 1011

12 bits

#1100 : 1100

13 bits

#1101 : 1101

14 bits

#1110 : 1110

15 bits

#1111 : 1111

16 bits

: others

8bits

End of enumeration elements list.

LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB first

#1 : 1

LSB first

End of enumeration elements list.

SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

A next-access delay of 1 RSPCK + 2 PCLK

#1 : 1

A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

An SSL negation delay of 1 RSPCK

#1 : 1

An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

An RSPCK delay of 1 RSPCK

#1 : 1

An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

End of enumeration elements list.


SPCMD5

SPI Command Register %s
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD5 SPCMD5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SSLKP SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data sampling on odd edge, data variation on even edge

#1 : 1

Data variation on odd edge, data sampling on even edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

RSPCK is low when idle

#1 : 1

RSPCK is high when idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

These bits select the base bit rate

#01 : 01

These bits select the base bit rate divided by 2

#10 : 10

These bits select the base bit rate divided by 4

#11 : 11

These bits select the base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

#100 : 100

SSL4

#101 : 101

SSL5

#110 : 110

SSL6

#111 : 111

SSL7

End of enumeration elements list.

SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate all SSL signals on completion of transfer

#1 : 1

Keep SSL signal level from the end of transfer until the beginning of the next access.

End of enumeration elements list.

SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

20 bits

#0001 : 0001

24 bits

#0010 : 0010

32 bits

#0011 : 0011

32 bits

#1000 : 1000

9 bits

#1001 : 1001

10 bits

#1010 : 1010

11 bits

#1011 : 1011

12 bits

#1100 : 1100

13 bits

#1101 : 1101

14 bits

#1110 : 1110

15 bits

#1111 : 1111

16 bits

: others

8bits

End of enumeration elements list.

LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB first

#1 : 1

LSB first

End of enumeration elements list.

SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

A next-access delay of 1 RSPCK + 2 PCLK

#1 : 1

A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

An SSL negation delay of 1 RSPCK

#1 : 1

An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

An RSPCK delay of 1 RSPCK

#1 : 1

An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

End of enumeration elements list.


SPCMD6

SPI Command Register %s
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD6 SPCMD6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SSLKP SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data sampling on odd edge, data variation on even edge

#1 : 1

Data variation on odd edge, data sampling on even edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

RSPCK is low when idle

#1 : 1

RSPCK is high when idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

These bits select the base bit rate

#01 : 01

These bits select the base bit rate divided by 2

#10 : 10

These bits select the base bit rate divided by 4

#11 : 11

These bits select the base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

#100 : 100

SSL4

#101 : 101

SSL5

#110 : 110

SSL6

#111 : 111

SSL7

End of enumeration elements list.

SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate all SSL signals on completion of transfer

#1 : 1

Keep SSL signal level from the end of transfer until the beginning of the next access.

End of enumeration elements list.

SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

20 bits

#0001 : 0001

24 bits

#0010 : 0010

32 bits

#0011 : 0011

32 bits

#1000 : 1000

9 bits

#1001 : 1001

10 bits

#1010 : 1010

11 bits

#1011 : 1011

12 bits

#1100 : 1100

13 bits

#1101 : 1101

14 bits

#1110 : 1110

15 bits

#1111 : 1111

16 bits

: others

8bits

End of enumeration elements list.

LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB first

#1 : 1

LSB first

End of enumeration elements list.

SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

A next-access delay of 1 RSPCK + 2 PCLK

#1 : 1

A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

An SSL negation delay of 1 RSPCK

#1 : 1

An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

An RSPCK delay of 1 RSPCK

#1 : 1

An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

End of enumeration elements list.


SPCMD7

SPI Command Register %s
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD7 SPCMD7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SSLKP SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data sampling on odd edge, data variation on even edge

#1 : 1

Data variation on odd edge, data sampling on even edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

RSPCK is low when idle

#1 : 1

RSPCK is high when idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

These bits select the base bit rate

#01 : 01

These bits select the base bit rate divided by 2

#10 : 10

These bits select the base bit rate divided by 4

#11 : 11

These bits select the base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

#100 : 100

SSL4

#101 : 101

SSL5

#110 : 110

SSL6

#111 : 111

SSL7

End of enumeration elements list.

SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate all SSL signals on completion of transfer

#1 : 1

Keep SSL signal level from the end of transfer until the beginning of the next access.

End of enumeration elements list.

SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

20 bits

#0001 : 0001

24 bits

#0010 : 0010

32 bits

#0011 : 0011

32 bits

#1000 : 1000

9 bits

#1001 : 1001

10 bits

#1010 : 1010

11 bits

#1011 : 1011

12 bits

#1100 : 1100

13 bits

#1101 : 1101

14 bits

#1110 : 1110

15 bits

#1111 : 1111

16 bits

: others

8bits

End of enumeration elements list.

LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB first

#1 : 1

LSB first

End of enumeration elements list.

SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

A next-access delay of 1 RSPCK + 2 PCLK

#1 : 1

A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

An SSL negation delay of 1 RSPCK

#1 : 1

An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

An RSPCK delay of 1 RSPCK

#1 : 1

An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

End of enumeration elements list.


SPPCR

RSPI Pin Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPPCR SPPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPLP SPLP2 MOIFV MOIFE Reserved Reserved

SPLP : RSPI Loopback
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Loopback mode (data is inverted for transmission)

End of enumeration elements list.

SPLP2 : RSPI Loopback 2
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Loopback mode (data is not inverted for transmission)

End of enumeration elements list.

MOIFV : MOSI Idle Fixed Value
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The level output on the MOSIn pin during MOSI idling corresponds to low.

#1 : 1

The level output on the MOSIn pin during MOSI idling corresponds to high.

End of enumeration elements list.

MOIFE : MOSI Idle Value Fixing Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

MOSI output value equals final data from previous transfer

#1 : 1

MOSI output value equals the value set in the MOIFV bit

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write


SPDCR2

SPI Data Control Register 2
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPDCR2 SPDCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BYSW SINV Reserved

BYSW : Byte Swap Operating Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte Swap Operating Mode disabled

#1 : 1

Byte Swap Operating Mode enabled

End of enumeration elements list.

SINV : Serial data invert bit
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not invert serial data

#1 : 1

Invert serial data.

End of enumeration elements list.

Reserved : These bits are read as 000000. The write value should be 000000.
bits : 2 - 6 (5 bit)
access : read-write


SPCR3

RSPI Control Register 3
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCR3 SPCR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ETXMD BFDS CENDIE Reserved Reserved

ETXMD : Extended Communication Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Full-duplex synchronous or transmit-only serial communications.

#1 : 1

Receive-only serial communications in slave mode (SPCR.MSTR bit = 0).

End of enumeration elements list.

BFDS : Between Burst Transfer Frames Delay Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer

#1 : 1

Delay between frames is not inserted in burst transfer.

End of enumeration elements list.

CENDIE : RSPI Communication End Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Communication end interrupt request is disabled.

#1 : 1

Communication end interrupt request is enabled.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write


SPSR

SPI Status Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPSR SPSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVRF IDLNF MODF PERF UDRF SPTEF CENDF SPRF

OVRF : Overrun Error Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No overrun error occurs

#1 : 1

An overrun error occurs

End of enumeration elements list.

IDLNF : SPI Idle Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

SPI is in the idle state

#1 : 1

SPI is in the transfer state

End of enumeration elements list.

MODF : Mode Fault Error Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Neither mode fault error nor underrun error occurs

#1 : 1

A mode fault error or an underrun error occurs.

End of enumeration elements list.

PERF : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No parity error occurs

#1 : 1

A parity error occurs

End of enumeration elements list.

UDRF : Underrun Error Flag(When MODF is 0, This bit is invalid.)
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

A mode fault error occurs (MODF=1)

#1 : 1

An underrun error occurs (MODF=1)

End of enumeration elements list.

SPTEF : SPI Transmit Buffer Empty Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Data found in the transmit buffer

#1 : 1

No data in the transmit buffer

End of enumeration elements list.

CENDF : Communication End Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

The RSPI is not communicating or communicating.

#1 : 1

The RSPI communication completed.

End of enumeration elements list.

SPRF : SPI Receive Buffer Full Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No valid data in SPDR

#1 : 1

Valid data found in SPDR

End of enumeration elements list.


SPPR

RSPI Parameter Read Register
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPPR SPPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFWID Reserved BUFNUM Reserved Reserved CMDNUM

BUFWID : Buffer Width check
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

16bit

#1 : 1

32bit

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write

BUFNUM : Buffer Number check
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#001 : 001

1 Buffer

#100 : 100

4 Buffer

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

CMDNUM : Command Number check
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#0001 : 0001

1 Command

#1000 : 1000

8 Command

End of enumeration elements list.


SPDR

SPI Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPDR SPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPDR

SPDR : SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR.
bits : 0 - 30 (31 bit)
access : read-write


SPDR_HA

SPI Data Register ( halfword access )
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : SPDR
reset_Mask : 0x0

SPDR_HA SPDR_HA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPDR_HA

SPDR_HA : SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA.
bits : 0 - 14 (15 bit)
access : read-write


SPSCR

SPI Sequence Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPSCR SPSCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPSLN Reserved

SPSLN : RSPI Sequence Length SpecificationThe order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

Length 1 SPDMDx x = 0->0->...

#001 : 001

Length 2 SPDMDx x = 0->1->0->...

#010 : 010

Length 3 SPDMDx x = 0->1->2->0->...

#011 : 011

Length 4 SPDMDx x = 0->1->2->3->0->...

#100 : 100

Length 5 SPDMDx x = 0->1->2->3->4->0->...

#101 : 101

Length 6 SPDMDx x = 0->1->2->3->4->5->0->...

#110 : 110

Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->...

#111 : 111

Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->...

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write


SPSSR

SPI Sequence Status Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPSSR SPSSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPCP SPECM Reserved Reserved

SPCP : RSPI Command Pointer
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

#000 : 000

SPCMD0

#001 : 001

SPCMD1

#010 : 010

SPCMD2

#011 : 011

SPCMD3

#100 : 100

SPCMD4

#101 : 101

SPCMD5

#110 : 110

SPCMD6

#111 : 111

SPCMD7

End of enumeration elements list.

SPECM : RSPI Error Command
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

#000 : 000

SPCMD0

#001 : 001

SPCMD1

#010 : 010

SPCMD2

#011 : 011

SPCMD3

#100 : 100

SPCMD4

#101 : 101

SPCMD5

#110 : 110

SPCMD6

#111 : 111

SPCMD7

End of enumeration elements list.

Reserved : This bit is read as 0.
bits : 7 - 6 (0 bit)
access : read-only

Reserved : This bit is read as 0.
bits : 7 - 6 (0 bit)
access : read-only


SPBR

SPI Bit Rate Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPBR SPBR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPR

SPR : SPBR sets the bit rate in master mode.
bits : 0 - 6 (7 bit)
access : read-write


SPDCR

SPI Data Control Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPDCR SPDCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPFC SLSEL SPRDTD SPLW SPBYT Reserved

SPFC : Number of Frames Specification
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

1 frame

#01 : 01

2 frames

#10 : 10

3 frames

#11 : 11

4 frames.

End of enumeration elements list.

SLSEL : SSL Pin Output Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

SSL2 to SSL7->output, SSL1->output

#01 : 01

SSL2 to SSL7->I/O, SSL1->I/O

#10 : 10

SSL2 to SSL7->I/O, SSL1->output

#11 : 11

Setting prohibited

End of enumeration elements list.

SPRDTD : RSPI Receive/Transmit Data Selection
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

SPDR values are read from the receive buffer

#1 : 1

SPDR values are read from the transmit buffer (but only if the transmit buffer is empty)

End of enumeration elements list.

SPLW : SPI Word Access/Halfword Access Specification
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

SPDR_HA is valid to access in halfwords

#1 : 1

SPDR is valid (to access in words).

End of enumeration elements list.

SPBYT : SPI Byte Access Specification
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

SPDR is accessed in word or longword (SPLW is valid)

#1 : 1

SPDR is accessed in byte (SPLW is invalid)

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write


SPCKD

SPI Clock Delay Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCKD SPCKD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SCKDL Reserved

SCKDL : RSPCK Delay Setting
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

1 RSPCK

#001 : 001

2 RSPCK

#010 : 010

3 RSPCK

#011 : 011

4 RSPCK

#100 : 100

5 RSPCK

#101 : 101

6 RSPCK

#110 : 110

7 RSPCK

#111 : 111

8 RSPCK

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write


SSLND

SPI Slave Select Negation Delay Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSLND SSLND read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLNDL Reserved

SLNDL : SSL Negation Delay Setting
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

1 RSPCK

#001 : 001

2 RSPCK

#010 : 010

3 RSPCK

#011 : 011

4 RSPCK

#100 : 100

5 RSPCK

#101 : 101

6 RSPCK

#110 : 110

7 RSPCK

#111 : 111

8 RSPCK

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write


SPND

SPI Next-Access Delay Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPND SPND read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPNDL Reserved

SPNDL : SPI Next-Access Delay Setting
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

1 RSPCK + 2 PCLK

#001 : 001

2 RSPCK + 2 PCLK

#010 : 010

3 RSPCK + 2 PCLK

#011 : 011

4 RSPCK + 2 PCLK

#100 : 100

5 RSPCK + 2 PCLK

#101 : 101

6 RSPCK + 2 PCLK

#110 : 110

7 RSPCK + 2 PCLK

#111 : 111

8 RSPCK + 2 PCLK

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write


SPCR2

SPI Control Register 2
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCR2 SPCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPPE SPOE SPIIE PTE SCKASE SPTDDL

SPPE : Parity Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not add the parity bit to transmit data and does not check the parity bit of receive data

#1 : 1

Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1)

End of enumeration elements list.

SPOE : Parity Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Selects even parity for use in transmission and reception

#1 : 1

Selects odd parity for use in transmission and reception

End of enumeration elements list.

SPIIE : SPI Idle Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the generation of idle interrupt requests

#1 : 1

Enables the generation of idle interrupt requests

End of enumeration elements list.

PTE : Parity Self-Testing
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the self-diagnosis function of the parity circuit

#1 : 1

Enables the self-diagnosis function of the parity circuit

End of enumeration elements list.

SCKASE : RSPCK Auto-Stop Function Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the RSPCK auto-stop function

#1 : 1

Enables the RSPCK auto-stop function

End of enumeration elements list.

SPTDDL : RSPI Transmit Data Delay
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#010 : 010

Same as above

#011 : 011

Same as above

#100 : 100

Same as above

#101 : 101

Same as above

#110 : 110

Same as above

#111 : 111

Same as above

End of enumeration elements list.



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