\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x804 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
Transfer Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMRM : Serial interface read mode select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
Standard Read
#001 : 001
Fast Read
#010 : 010
Fast Read Dual Output
#011 : 011
Fast Read Dual I/O
#100 : 100
Fast Read Quad Output
#101 : 101
Fast Read Quad I/O
: Others
Setting prohibited
End of enumeration elements list.
SFMSE : QSSL extension function select after SPI bus access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not extend QSSL
#01 : 01
Extend QSSL by 33 QSPCLK
#10 : 10
Extend QSSL by 129 QSPCLK
#11 : 11
Extend QSSL infinitely
End of enumeration elements list.
SFMPFE : Prefetch function select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable function
#1 : 1
Enable function
End of enumeration elements list.
SFMPAE : Function select for stopping prefetch at locations other than on byte boundaries
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable function
#1 : 1
Enable function
End of enumeration elements list.
SFMMD3 : SPI mode select. Initial value determined by input to CFGMD3
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
SPI mode 0
#1 : 1
SPI mode 3
End of enumeration elements list.
SFMOEX : Extension select for the I/O buffer output enable signal for the serial interface
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not extend
#1 : 1
Extend by 1 QSPCLK
End of enumeration elements list.
SFMOHW : Hold time adjustment for serial transmission
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not extend high-level width of QSPCLK during transmission
#1 : 1
Extend high-level width of QSPCLK by 1 PCLKH during transmission
End of enumeration elements list.
SFMOSW : Setup time adjustment for serial transmission
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not extend low-level width of QSPCLK during transmission
#1 : 1
Extend low-level width of QSPCLK by 1 PCLKH during transmission
End of enumeration elements list.
SFMCCE : Read instruction code select
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Set default instruction code for each instruction
#1 : 1
Write instruction code in the SFMSIC register
End of enumeration elements list.
Communication Port Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMD : Port select for direct communication with the SPI bus
bits : 0 - 6 (7 bit)
access : read-write
Communication Mode Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOM : Mode select for communication with the SPI bus
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
ROM access mode
#1 : 1
Direct communication mode
End of enumeration elements list.
Communication Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMBSY : SPI bus cycle completion state in direct communication
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No serial transfer being processed
#1 : 1
Serial transfer being processed
End of enumeration elements list.
EROMR : ROM access detection status in direct communication mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
ROM access not detected
#1 : 1
ROM access detected
End of enumeration elements list.
Instruction Code Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMCIC : Serial flash instruction code to substitute
bits : 0 - 6 (7 bit)
access : read-write
Address Mode Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMAS : Number of address bytes select for the serial interface
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
1 byte
#01 : 01
2 bytes
#10 : 10
3 bytes
#11 : 11
4 bytes
End of enumeration elements list.
SFM4BC : Default instruction code select, when the serial interface address width is 4 bytes
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not use 4-byte address read instruction code
#1 : 1
Use 4-byte address read instruction code
End of enumeration elements list.
Dummy Cycle Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMDN : Number of dummy cycles select for Fast Read instructions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
Default dummy cycles for each instruction: - Fast Read Quad I/O: 6 QSPCLK - Fast Read Quad Output: 8 QSPCLK - Fast Read Dual I/O: 4 QSPCLK - Fast Read Dual Output: 8 QSPCLK - Fast Read: 8 QSPCLK
0x1 : 0x1
3 QSPCLK
0x2 : 0x2
4 QSPCLK
0x3 : 0x3
5 QSPCLK
0x4 : 0x4
6 QSPCLK
0x5 : 0x5
7 QSPCLK
0x6 : 0x6
8 QSPCLK
0x7 : 0x7
9 QSPCLK
0x8 : 0x8
10 QSPCLK
0x9 : 0x9
11 QSPCLK
0xa : 0xA
12 QSPCLK
0xb : 0xB
13 QSPCLK
0xc : 0xC
14 QSPCLK
0xd : 0xD
15 QSPCLK
0xe : 0xE
16 QSPCLK
0xf : 0xF
17 QSPCLK
End of enumeration elements list.
SFMXST : XIP mode status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Normal (non-XIP) mode
#1 : 1
XIP mode
End of enumeration elements list.
SFMXEN : XIP mode permission
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibit XIP mode
#1 : 1
Permit XIP mode
End of enumeration elements list.
SFMXD : Mode data for serial flash (Controls XIP mode.)
bits : 8 - 14 (7 bit)
access : read-write
SPI Protocol Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMSPI : SPI protocol select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Single/Extended SPI protocol
#01 : 01
Dual SPI protocol
#10 : 10
Quad SPI protocol
#11 : 11
Setting prohibited
End of enumeration elements list.
SFMSDE : Minimum time select for input/output switch, when Dual SPI or Quad SPI protocol is selected and in standard read mode
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not allocate minimum switch time
#1 : 1
Allocate minimum switch time equivalent to 1 QSPCLK
End of enumeration elements list.
Port Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMWPL : WP pin level specification
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Low level
#1 : 1
High level
End of enumeration elements list.
Chip Selection Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMSW : Minimum high-level width select for QSSL signal
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
1 QSPCLK
0x1 : 0x1
2 QSPCLK
0x2 : 0x2
3 QSPCLK
0x3 : 0x3
4 QSPCLK
0x4 : 0x4
5 QSPCLK
0x5 : 0x5
6 QSPCLK
0x6 : 0x6
7 QSPCLK
0x7 : 0x7
8 QSPCLK
0x8 : 0x8
9 QSPCLK
0x9 : 0x9
10 QSPCLK
0xa : 0xA
11 QSPCLK
0xb : 0xB
12 QSPCLK
0xc : 0xC
13 QSPCLK
0xd : 0xD
14 QSPCLK
0xe : 0xE
15 QSPCLK
0xf : 0xF
16 QSPCLK
End of enumeration elements list.
SFMSHD : QSSL signal release timing select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Release QSSL 0.5 QSPCLK cycles after the last rising edge of QSPCLK
#1 : 1
Release QSSL 1.5 QSPCLK cycles after the last rising edge of QSPCLK
End of enumeration elements list.
SFMSLD : QSSL signal output timing select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output QSSL 0.5 QSPCLK cycles before the first rising edge of QSPCLK
#1 : 1
Output QSSL 1.5 QSPCLK cycles before the first rising edge of QSPCLK
End of enumeration elements list.
Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFMDV : Serial interface reference cycle select. (Pay attention to irregularities.)
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
2 PCLKH
0x01 : 0x01
3 PCLKH (multiplied by an odd number)
0x02 : 0x02
4 PCLKH
0x03 : 0x03
5 PCLKH (multiplied by an odd number)
0x04 : 0x04
6 PCLKH
0x05 : 0x05
7 PCLKH (multiplied by an odd number)
0x06 : 0x06
8 PCLKH
0x07 : 0x07
9 PCLKH (multiplied by an odd number)
0x08 : 0x08
10 PCLKH
0x09 : 0x09
11 PCLKH (multiplied by an odd number)
0x0a : 0x0A
12 PCLKH
0x0b : 0x0B
13 PCLKH (multiplied by an odd number)
0x0c : 0x0C
14 PCLKH
0x0d : 0x0D
15 PCLKH (multiplied by an odd number)
0x0e : 0x0E
16 PCLKH
0x0f : 0x0F
17 PCLKH (multiplied by an odd number)
0x10 : 0x10
18 PCLKH
0x11 : 0x11
20 PCLKH
0x12 : 0x12
22 PCLKH
0x13 : 0x13
24 PCLKH
0x14 : 0x14
26 PCLKH
0x15 : 0x15
28 PCLKH
0x16 : 0x16
30 PCLKH
0x17 : 0x17
32 PCLKH
0x18 : 0x18
34 PCLKH
0x19 : 0x19
36 PCLKH
0x1a : 0x1A
38 PCLKH
0x1b : 0x1B
40 PCLKH
0x1c : 0x1C
42 PCLKH
0x1d : 0x1D
44 PCLKH
0x1e : 0x1E
46 PCLKH
0x1f : 0x1F
48 PCLKH
End of enumeration elements list.
SFMDTY : Duty ratio correction function select for the QSPCLK signal
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Make no correction
#1 : 1
Delay the rising of the QSPCLK signal by 0.5 PCLKH cycles (Valid when PCLKH is multiplied by an odd number.)
End of enumeration elements list.
External QSPI Address Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QSPI_EXT : Bank switching address
bits : 26 - 30 (5 bit)
access : read-write
Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PFCNT : Number of bytes of prefetched data
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0x00 : 0x00
0 byte
0x01 : 0x01
1 byte
0x02 : 0x02
2 bytes
0x03 : 0x03
3 bytes
0x04 : 0x04
4 bytes
0x05 : 0x05
5 bytes
0x06 : 0x06
6 bytes
0x07 : 0x07
7 bytes
0x08 : 0x08
8 bytes
0x09 : 0x09
9 bytes
0x0a : 0x0A
10 bytes
0x0b : 0x0B
11 bytes
0x0c : 0x0C
12 bytes
0x0d : 0x0D
13 bytes
0x0e : 0x0E
14 bytes
0x0f : 0x0F
15 bytes
0x10 : 0x10
16 bytes
0x11 : 0x11
17 bytes
0x12 : 0x12
18 bytes
: Others
Reserved
End of enumeration elements list.
PFFUL : Prefetch buffer state
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Prefetch buffer has free space
#1 : 1
Prefetch buffer is full
End of enumeration elements list.
PFOFF : Prefetch function operating state
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Prefetch function operating
#1 : 1
Prefetch function not enabled or not operating
End of enumeration elements list.
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