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RMPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x108 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x200 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x500 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x504 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x508 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x600 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC00 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC18 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC20 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC24 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD00 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD04 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD14 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

MMPUOAD

MMPUENDMAC

MMPUENPTDMAC

MMPURPTDMAC

MMPURPTDMAC_SEC

MMPUACDMAC0

MMPUSDMAC0

MMPUEDMAC0

MMPUACDMAC1

MMPUSDMAC1

MMPUEDMAC1

MMPUACDMAC2

MMPUSDMAC2

MMPUEDMAC2

MMPUACDMAC3

MMPUSDMAC3

MMPUEDMAC3

MMPUACDMAC4

MMPUSDMAC4

MMPUEDMAC4

MMPUACDMAC5

MMPUSDMAC5

MMPUEDMAC5

MMPUACDMAC6

MMPUSDMAC6

MMPUEDMAC6

MMPUACDMAC7

MMPUSDMAC7

MMPUEDMAC7

MMPUOADPT

MMPUENEDMAC

MMPUENPTEDMAC

MMPURPTEDMAC

MMPUACEDMAC0

MMPUSEDMAC0

MMPUACEDMAC1

MMPUSEDMAC1

MMPUACEDMAC2

MMPUSEDMAC2

MMPUACEDMAC3

MMPUSEDMAC3

SMPUCTL

SMPUMBIU

SMPUFBIU

SMPUSRAM0

SMPUP0BIU

SMPUP2BIU

MSPMPUOAD

MSPMPUCTL

MSPMPUPT

MSPMPUSA

MSPMPUEA

PSPMPUOAD

PSPMPUCTL

PSPMPUPT

PSPMPUSA

PSPMPUEA


MMPUOAD

MMPU Operation After Detection Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUOAD MMPUOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OAD KEY

OAD : Operation after detection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Reset

End of enumeration elements list.

KEY : This bit enables or disables writes to the OAD bit.
bits : 8 - 14 (7 bit)
access : write-only


MMPUENDMAC

MMPU Enable Register for DMAC
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUENDMAC MMPUENDMAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE KEY

ENABLE : Bus Master MPU of DMAC enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus Master MPU of DMAC is disabled.

#1 : 1

Bus Master MPU of DMAC is enabled.

End of enumeration elements list.

KEY : These bits enable or disable writes to the ENABLE bit.
bits : 8 - 14 (7 bit)
access : write-only


MMPUENPTDMAC

MMPU Enable Protect Register for DMAC
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUENPTDMAC MMPUENPTDMAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT KEY

PROTECT : Protection of register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

MMPUENDMAC register writes are possible.

#1 : 1

MMPUENDMAC register writes are protected. Read is possible.

End of enumeration elements list.

KEY : These bits enable or disable writes to the PROTECT bit.
bits : 8 - 14 (7 bit)
access : write-only


MMPURPTDMAC

MMPU Regions Protect Register for DMAC
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPURPTDMAC MMPURPTDMAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT KEY

PROTECT : Protection of register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus Master MPU register for DMAC writing is possible.

#1 : 1

Bus Master MPU register for DMAC writing is protected. Read is possible.

End of enumeration elements list.

KEY : These bits enable or disable writes to the PROTECT bit.
bits : 8 - 14 (7 bit)
access : write-only


MMPURPTDMAC_SEC

MMPU Regions Protect register for DMAC Secure
address_offset : 0x10C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPURPTDMAC_SEC MMPURPTDMAC_SEC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT KEY

PROTECT : Protection of register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus master MPU register for DMAC secure writes are possible.

#1 : 1

Bus master MPU register for DMAC secure writes are protected. Read is possible.

End of enumeration elements list.

KEY : These bits enable or disable writes to the PROTECT bit.
bits : 8 - 14 (7 bit)
access : write-only


MMPUACDMAC0

MMPU Access Control Register for DMAC
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACDMAC0 MMPUACDMAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC Region n unit is disabled

#1 : 1

DMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSDMAC0

MMPU Start Address Register for DMAC
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSDMAC0 MMPUSDMAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUEDMAC0

MMPU End Address Register for DMAC
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUEDMAC0 MMPUEDMAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUE

MMPUE : Region end address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUACDMAC1

MMPU Access Control Register for DMAC
address_offset : 0x210 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACDMAC1 MMPUACDMAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC Region n unit is disabled

#1 : 1

DMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSDMAC1

MMPU Start Address Register for DMAC
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSDMAC1 MMPUSDMAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUEDMAC1

MMPU End Address Register for DMAC
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUEDMAC1 MMPUEDMAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUE

MMPUE : Region end address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUACDMAC2

MMPU Access Control Register for DMAC
address_offset : 0x220 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACDMAC2 MMPUACDMAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC Region n unit is disabled

#1 : 1

DMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSDMAC2

MMPU Start Address Register for DMAC
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSDMAC2 MMPUSDMAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUEDMAC2

MMPU End Address Register for DMAC
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUEDMAC2 MMPUEDMAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUE

MMPUE : Region end address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUACDMAC3

MMPU Access Control Register for DMAC
address_offset : 0x230 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACDMAC3 MMPUACDMAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC Region n unit is disabled

#1 : 1

DMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSDMAC3

MMPU Start Address Register for DMAC
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSDMAC3 MMPUSDMAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUEDMAC3

MMPU End Address Register for DMAC
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUEDMAC3 MMPUEDMAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUE

MMPUE : Region end address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUACDMAC4

MMPU Access Control Register for DMAC
address_offset : 0x240 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACDMAC4 MMPUACDMAC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC Region n unit is disabled

#1 : 1

DMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSDMAC4

MMPU Start Address Register for DMAC
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSDMAC4 MMPUSDMAC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUEDMAC4

MMPU End Address Register for DMAC
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUEDMAC4 MMPUEDMAC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUE

MMPUE : Region end address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUACDMAC5

MMPU Access Control Register for DMAC
address_offset : 0x250 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACDMAC5 MMPUACDMAC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC Region n unit is disabled

#1 : 1

DMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSDMAC5

MMPU Start Address Register for DMAC
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSDMAC5 MMPUSDMAC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUEDMAC5

MMPU End Address Register for DMAC
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUEDMAC5 MMPUEDMAC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUE

MMPUE : Region end address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUACDMAC6

MMPU Access Control Register for DMAC
address_offset : 0x260 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACDMAC6 MMPUACDMAC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC Region n unit is disabled

#1 : 1

DMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSDMAC6

MMPU Start Address Register for DMAC
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSDMAC6 MMPUSDMAC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUEDMAC6

MMPU End Address Register for DMAC
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUEDMAC6 MMPUEDMAC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUE

MMPUE : Region end address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUACDMAC7

MMPU Access Control Register for DMAC
address_offset : 0x270 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACDMAC7 MMPUACDMAC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC Region n unit is disabled

#1 : 1

DMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSDMAC7

MMPU Start Address Register for DMAC
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSDMAC7 MMPUSDMAC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUEDMAC7

MMPU End Address Register for DMAC
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUEDMAC7 MMPUEDMAC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUE

MMPUE : Region end address register
bits : 5 - 30 (26 bit)
access : read-write


MMPUOADPT

MMPU Operation After Detection Protect Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUOADPT MMPUOADPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT KEY

PROTECT : Protection of register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

MMPUOAD register writes are possible.

#1 : 1

MMPUOAD register writes are protected. Read is possible.

End of enumeration elements list.

KEY : Key code
bits : 8 - 14 (7 bit)
access : write-only


MMPUENEDMAC

MMPU Enable Register for EDMAC
address_offset : 0x500 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUENEDMAC MMPUENEDMAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE KEY

ENABLE : Bus Master MPU of EDMAC enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus Master MPU of EDMAC is disabled.

#1 : 1

Bus Master MPU of EDMAC is enabled.

End of enumeration elements list.

KEY : These bits enable or disable writes to the ENABLE bit.
bits : 8 - 14 (7 bit)
access : write-only


MMPUENPTEDMAC

MMPU Enable Protect Register for EDMAC
address_offset : 0x504 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUENPTEDMAC MMPUENPTEDMAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT KEY

PROTECT : Protection of register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

MMPUENEDMAC register writes are possible.

#1 : 1

MMPUENEDMAC register writes are protected. Read is possible.

End of enumeration elements list.

KEY : These bits enable or disable writes to the PROTECT bit.
bits : 8 - 14 (7 bit)
access : write-only


MMPURPTEDMAC

MMPU Regions Protect Register for EDMAC
address_offset : 0x508 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPURPTEDMAC MMPURPTEDMAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT KEY

PROTECT : Protection of register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus Master MPU register for EDMAC writing is possible.

#1 : 1

Bus Master MPU register for EDMAC writing is protected. Read is possible.

End of enumeration elements list.

KEY : This bit is used to enable or disable writing of the PROTECT bit.
bits : 8 - 14 (7 bit)
access : write-only


MMPUACEDMAC0

MMPU Access Control Register for EDMAC
address_offset : 0x600 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACEDMAC0 MMPUACEDMAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

EDMAC Region n unit is disabled

#1 : 1

EDMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSEDMAC0

MMPU Start Address Register for EDMAC
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSEDMAC0 MMPUSEDMAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register for EDMAC
bits : 5 - 30 (26 bit)
access : read-write


MMPUACEDMAC1

MMPU Access Control Register for EDMAC
address_offset : 0x610 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACEDMAC1 MMPUACEDMAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

EDMAC Region n unit is disabled

#1 : 1

EDMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSEDMAC1

MMPU Start Address Register for EDMAC
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSEDMAC1 MMPUSEDMAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register for EDMAC
bits : 5 - 30 (26 bit)
access : read-write


MMPUACEDMAC2

MMPU Access Control Register for EDMAC
address_offset : 0x620 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACEDMAC2 MMPUACEDMAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

EDMAC Region n unit is disabled

#1 : 1

EDMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSEDMAC2

MMPU Start Address Register for EDMAC
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSEDMAC2 MMPUSEDMAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register for EDMAC
bits : 5 - 30 (26 bit)
access : read-write


MMPUACEDMAC3

MMPU Access Control Register for EDMAC
address_offset : 0x630 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUACEDMAC3 MMPUACEDMAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RP WP

ENABLE : Region enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

EDMAC Region n unit is disabled

#1 : 1

EDMAC Region n unit is enabled

End of enumeration elements list.

RP : Read protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read permission

#1 : 1

Read protection

End of enumeration elements list.

WP : Write protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write permission

#1 : 1

Write protection

End of enumeration elements list.


MMPUSEDMAC3

MMPU Start Address Register for EDMAC
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMPUSEDMAC3 MMPUSEDMAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMPUS

MMPUS : Region start address register for EDMAC
bits : 5 - 30 (26 bit)
access : read-write


SMPUCTL

Slave MPU Control Register
address_offset : 0xC00 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPUCTL SMPUCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OAD PROTECT KEY

OAD : Operation After Detection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Reset

End of enumeration elements list.

PROTECT : Protection of Register
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

All bus slave register writes are permitted

#1 : 1

All bus slave register writes are protected. Reads are permitted

End of enumeration elements list.

KEY : Key Code
bits : 8 - 14 (7 bit)
access : read-write


SMPUMBIU

Access Control Register for Memory Bus 1
address_offset : 0xC10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPUMBIU SMPUMBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPGRPA WPGRPA

RPGRPA : Master MPU Group A Read Protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection read for master MPU group A disabled

#1 : 1

Memory protection read for master MPU group A enabled

End of enumeration elements list.

WPGRPA : Master MPU Group A Write Protection
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection write for master MPU group A disabled

#1 : 1

Memory protection write for master MPU group A enabled

End of enumeration elements list.


SMPUFBIU

Access Control Register for Internal Peripheral Bus 9
address_offset : 0xC14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPUFBIU SMPUFBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPCPU WPCPU RPGRPA WPGRPA

RPCPU : CPU Read Protection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for CPU read disabled

#1 : 1

Memory protection for CPU read enabled

End of enumeration elements list.

WPCPU : CPU Write Protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for CPU write disabled

#1 : 1

Memory protection for CPU write enabled

End of enumeration elements list.

RPGRPA : Master MPU Group A Read Protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for master MPU group A read disabled

#1 : 1

Memory protection for master MPU group A read enabled

End of enumeration elements list.

WPGRPA : Master MPU Group A Write Protection
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for master MPU group A write disabled

#1 : 1

Memory protection for master MPU group A write enabled

End of enumeration elements list.


SMPUSRAM0

Access Control Register for Memory Bus 4
address_offset : 0xC18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPUSRAM0 SMPUSRAM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPCPU WPCPU RPGRPA WPGRPA

RPCPU : CPU Read Protection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for CPU read disabled

#1 : 1

Memory protection for CPU read enabled

End of enumeration elements list.

WPCPU : CPU Write Protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for CPU write disabled

#1 : 1

Memory protection for CPU write enabled

End of enumeration elements list.

RPGRPA : Master MPU Group A Read Protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for master MPU group A read disabled

#1 : 1

Memory protection for master MPU group A read enabled

End of enumeration elements list.

WPGRPA : Master MPU Group A Write Protection
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for master MPU group A write disabled

#1 : 1

Memory protection for master MPU group A write enabled

End of enumeration elements list.


SMPUP0BIU

Access Control Register for Internal Peripheral Bus 1
address_offset : 0xC20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPUP0BIU SMPUP0BIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPCPU WPCPU RPGRPA WPGRPA

RPCPU : CPU Read Protection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for CPU read disabled

#1 : 1

Memory protection for CPU read enabled

End of enumeration elements list.

WPCPU : CPU Write Protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for CPU write disabled

#1 : 1

Memory protection for CPU write enabled

End of enumeration elements list.

RPGRPA : Master MPU Group A Read Protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for master MPU group A read disabled

#1 : 1

Memory protection for master MPU group A read enabled

End of enumeration elements list.

WPGRPA : Master MPU Group A Write Protection
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for master MPU group A write disabled

#1 : 1

Memory protection for master MPU group A write enabled

End of enumeration elements list.


SMPUP2BIU

Access Control Register for Internal Peripheral Bus 3
address_offset : 0xC24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPUP2BIU SMPUP2BIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPCPU WPCPU RPGRPA WPGRPA

RPCPU : CPU Read Protection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for CPU read disabled

#1 : 1

Memory protection for CPU read enabled

End of enumeration elements list.

WPCPU : CPU Write Protection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for CPU write disabled

#1 : 1

Memory protection for CPU write enabled

End of enumeration elements list.

RPGRPA : Master MPU Group A Read Protection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for master MPU group A read disabled

#1 : 1

Memory protection for master MPU group A read enabled

End of enumeration elements list.

WPGRPA : Master MPU Group A Write Protection
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Memory protection for master MPU group A write disabled

#1 : 1

Memory protection for master MPU group A write enabled

End of enumeration elements list.


MSPMPUOAD

Stack Pointer Monitor Operation After Detection Register
address_offset : 0xD00 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSPMPUOAD MSPMPUOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OAD KEY

OAD : Operation after Detection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Reset

End of enumeration elements list.

KEY : Key Code
bits : 8 - 14 (7 bit)
access : read-write


MSPMPUCTL

Stack Pointer Monitor Access Control Register
address_offset : 0xD04 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSPMPUCTL MSPMPUCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE ERROR

ENABLE : Stack Pointer Monitor Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stack pointer monitor is disabled

#1 : 1

Stack pointer monitor is enabled

End of enumeration elements list.

ERROR : Stack Pointer Monitor Error Flag
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stack pointer has not overflowed or underflowed

#1 : 1

Stack pointer has overflowed or underflowed

End of enumeration elements list.


MSPMPUPT

Stack Pointer Monitor Protection Register
address_offset : 0xD06 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSPMPUPT MSPMPUPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT KEY

PROTECT : Protection of Register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stack pointer monitor register writes are permitted.

#1 : 1

Stack pointer monitor register writes are protected. Reads are permitted

End of enumeration elements list.

KEY : Key Code
bits : 8 - 14 (7 bit)
access : read-write


MSPMPUSA

Main Stack Pointer (MSP) Monitor Start Address Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSPMPUSA MSPMPUSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSPMPUSA

MSPMPUSA : Region Start Address
bits : 0 - 30 (31 bit)
access : read-write


MSPMPUEA

Main Stack Pointer (MSP) Monitor End Address Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSPMPUEA MSPMPUEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSPMPUEA

MSPMPUEA : Region End Address
bits : 0 - 30 (31 bit)
access : read-write


PSPMPUOAD

Stack Pointer Monitor Operation After Detection Register
address_offset : 0xD10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSPMPUOAD PSPMPUOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OAD KEY

OAD : Operation after Detection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Reset

End of enumeration elements list.

KEY : Key Code
bits : 8 - 14 (7 bit)
access : read-write


PSPMPUCTL

Stack Pointer Monitor Access Control Register
address_offset : 0xD14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSPMPUCTL PSPMPUCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE ERROR

ENABLE : Stack Pointer Monitor Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stack pointer monitor is disabled

#1 : 1

Stack pointer monitor is enabled

End of enumeration elements list.

ERROR : Stack Pointer Monitor Error Flag
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stack pointer has not overflowed or underflowed

#1 : 1

Stack pointer has overflowed or underflowed

End of enumeration elements list.


PSPMPUPT

Stack Pointer Monitor Protection Register
address_offset : 0xD16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSPMPUPT PSPMPUPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT KEY

PROTECT : Protection of Register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stack pointer monitor register writes are permitted.

#1 : 1

Stack pointer monitor register writes are protected. Reads are permitted

End of enumeration elements list.

KEY : Key Code
bits : 8 - 14 (7 bit)
access : read-write


PSPMPUSA

Process Stack Pointer (PSP) Monitor Start Address Register
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSPMPUSA PSPMPUSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSPMPUSA

PSPMPUSA : Region Start Address
bits : 0 - 30 (31 bit)
access : read-write


PSPMPUEA

Process Stack Pointer (PSP) Monitor End Address Register
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSPMPUEA PSPMPUEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSPMPUEA

PSPMPUEA : Region End Address
bits : 0 - 30 (31 bit)
access : read-write



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