\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x34 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x7C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Device Command Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVCMD0 : Device Command data
bits : 0 - 6 (7 bit)
access : read-write
DVCMD1 : Device Command data
bits : 8 - 14 (7 bit)
access : read-write
Device Size Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DV1SZ : Device 1 size setting
bits : 0 - 28 (29 bit)
access : read-write
DV1TYP : Device 1 type setting
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
flash on device 1
#01 : 01
RAM on device 1
#10 : 10
no connection on device 1
#11 : 11
forbidden
End of enumeration elements list.
Memory Delay Trim Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DV0DEL : Device 0 delay setting
bits : 0 - 6 (7 bit)
access : read-write
DQSERAM : OM_DQS enable counter
bits : 8 - 10 (3 bit)
access : read-write
DQSESOPI : OM_DQS enable counter
bits : 12 - 14 (3 bit)
access : read-write
DV1DEL : Device 1 delay setting
bits : 16 - 22 (7 bit)
access : read-write
DQSEDOPI : OM_DQS enable counter
bits : 24 - 26 (3 bit)
access : read-write
Auto-Calibration Timer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTP : Automatic calibration cycle time setting
bits : 0 - 30 (31 bit)
access : read-write
Auto-Calibration Address Register 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAD0 : Automatic calibration address
bits : 0 - 30 (31 bit)
access : read-write
Auto-Calibration Address Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAD1 : Automatic calibration address
bits : 0 - 30 (31 bit)
access : read-write
Device Memory Map Read Chip Select Timing Setting Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRW0 : Device 0 single continuous read waiting cycle setting in PCLKA units
bits : 0 - 5 (6 bit)
access : read-write
CTR0 : Device 0 single continuous read mode setting
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single continuous read mode is disabled for device 0.
#1 : 1
Single continuous read mode is enabled for device 0.
End of enumeration elements list.
DVRDCMD0 : Device 0 Command execution interval setting
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
2 clock cycles
#001 : 001
5 clock cycles
#010 : 010
7 clock cycles
#011 : 011
9 clock cycles
#100 : 100
11 clock cycles
#101 : 101
13 clock cycles
#110 : 110
15 clock cycles
#111 : 111
17 clock cycles
End of enumeration elements list.
DVRDHI0 : Device 0 select signal pull-up timing setting
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
#000 : 000
Setting prohibit
#001 : 001
Setting prohibit
#010 : 010
Setting prohibit
#011 : 011
Setting prohibit (DOPI mode) 5 clock cycles (Other mode)
#100 : 100
Setting prohibit (DOPI mode) 6 clock cycles (Other mode)
#101 : 101
6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode)
#110 : 110
7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode)
#111 : 111
8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode)
End of enumeration elements list.
DVRDLO0 : Device 0 select signal pull-down timing setting
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Setting prohibit
#01 : 01
2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode)
#10 : 10
3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode)
#11 : 11
4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode)
End of enumeration elements list.
CTRW1 : Device 1 single continuous read waiting cycle setting in PCLKA units
bits : 16 - 21 (6 bit)
access : read-write
CTR1 : Device 1 single continuous read mode setting
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single continuous read mode is disabled for device 1.
#1 : 1
Single continuous read mode is enabled for device 1.
End of enumeration elements list.
DVRDCMD1 : Device 1 Command execution interval
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#000 : 000
2 clock cycles
#001 : 001
5 clock cycles
#010 : 010
7 clock cycles
#011 : 011
9 clock cycles
#100 : 100
11 clock cycles
#101 : 101
13 clock cycles
#110 : 110
15 clock cycles
#111 : 111
17 clock cycles
End of enumeration elements list.
DVRDHI1 : Device 1 select signal High timing setting
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#000 : 000
Setting prohibit
#001 : 001
Setting prohibit
#010 : 010
Setting prohibit
#011 : 011
Setting prohibit (DOPI mode) 5 clock cycles (Other mode)
#100 : 100
Setting prohibit (DOPI mode) 6 clock cycles (Other mode)
#101 : 101
6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode)
#110 : 110
7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode)
#111 : 111
8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode)
End of enumeration elements list.
DVRDLO1 : Device 1 select signal pull-down timing setting
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
Setting prohibited
#01 : 01
2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode)
#10 : 10
3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode)
#11 : 11
4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode)
End of enumeration elements list.
Device Memory Map Write Chip Select Timing Setting Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTWW0 : Device 0 single continuous write waiting cycle setting in PCLKA units
bits : 0 - 5 (6 bit)
access : read-write
CTW0 : Device 0 single continuous write mode setting
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single continuous write mode is disabled for device 0
#1 : 1
Single continuous write mode is enabled for device 0
End of enumeration elements list.
DVWCMD0 : Device 0 Command execution interval setting
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
2 clock cycles
#001 : 001
5 clock cycles
#010 : 010
7 clock cycles
#011 : 011
9 clock cycles
#100 : 100
11 clock cycles
#101 : 101
13 clock cycles
#110 : 110
15 clock cycles
#111 : 111
17 clock cycles
End of enumeration elements list.
DVWHI0 : Device 0 select signal pull-up timing setting
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
#000 : 000
1.5 clock cycles (DOPI mode) 2 clock cycles (Other mode)
#001 : 001
2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode)
#010 : 010
3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode)
#011 : 011
4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode)
#100 : 100
5.5 clock cycles (DOPI mode) 6 clock cycles (Other mode)
#101 : 101
6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode)
#110 : 110
7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode)
#111 : 111
8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode)
End of enumeration elements list.
DVWLO0 : Device 0 select signal pull-down timing setting
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Setting prohibit
#01 : 01
2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode)
#10 : 10
3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode)
#11 : 11
4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode)
End of enumeration elements list.
CTWW1 : Device 1 single continuous write waiting cycle setting in PCLKA units
bits : 16 - 21 (6 bit)
access : read-write
CTW1 : Device 1 single continuous write mode setting
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single continuous write mode is disabled for device 1
#1 : 1
Single continuous write mode is enabled for device 1
End of enumeration elements list.
DVWCMD1 : Device 1 Command execution interval setting
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#000 : 000
setting prohibited
#001 : 001
5 clock cycles
#010 : 010
7 clock cycles
#011 : 011
9 clock cycles
#100 : 100
11 clock cycles
#101 : 101
13 clock cycles
#110 : 110
15 clock cycles
#111 : 111
17 clock cycles
End of enumeration elements list.
DVWHI1 : Device 1 select signal pull-up timing setting
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#000 : 000
1.5 clock cycles (DOPI mode) 2 clock cycles (Other mode)
#001 : 001
2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode)
#010 : 010
3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode)
#011 : 011
4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode)
#100 : 100
5.5 clock cycles (DOPI mode) 6 clock cycles (Other mode)
#101 : 101
6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode)
#110 : 110
7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode)
#111 : 111
8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode)
End of enumeration elements list.
DVWLO1 : Device 1 select signal pull-down timing setting
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
Setting prohibit
#01 : 01
2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode)
#10 : 10
3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode)
#11 : 11
4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode)
End of enumeration elements list.
Device Chip Select Timing Setting Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVSELCMD : Device Command execution interval setting
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
2 clock cycles
#001 : 001
5 clock cycles
#010 : 010
7 clock cycles
#011 : 011
9 clock cycles
#100 : 100
11 clock cycles
#101 : 101
13 clock cycles
#110 : 110
15 clock cycles
#111 : 111
17 clock cycles
End of enumeration elements list.
DVSELHI : Device select signal pull-up timing setting
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
#000 : 000
Setting prohibited
#001 : 001
Setting prohibited
#010 : 010
Setting prohibited
#011 : 011
Setting prohibited (DOPI mode) 5 clock cycles (Other mode)
#100 : 100
Setting prohibited (DOPI mode) 6 clock cycles (Other mode)
#101 : 101
6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode)
#110 : 110
7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode)
#111 : 111
8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode)
End of enumeration elements list.
DVSELLO : Device select signal pull-down timing setting
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Setting prohibit
#01 : 01
2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode)
#10 : 10
3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode)
#11 : 11
4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode)
End of enumeration elements list.
Device Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVAD0 : Device Address data 0
bits : 0 - 6 (7 bit)
access : read-write
DVAD1 : Device Address data 1
bits : 8 - 14 (7 bit)
access : read-write
DVAD2 : Device Address data 2
bits : 16 - 22 (7 bit)
access : read-write
DVAD3 : Device Address data 3
bits : 24 - 30 (7 bit)
access : read-write
Controller and Device Setting Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DV0TTYP : Device0_transfer_type setting
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
SPI mode
#01 : 01
SOPI mode
#10 : 10
DOPI mode
#11 : 11
Setting prohibited
End of enumeration elements list.
DV1TTYP : Device1_transfer_type setting
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : 00
SPI mode
#01 : 01
SOPI mode
#10 : 10
DOPI mode
#11 : 11
Setting prohibited
End of enumeration elements list.
DV0PC : Device0_memory precycle setting
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DV1PC : Device1_memory precycle setting
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ACMEME0 : Automatic calibration memory enable setting for device 0
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ACMEME1 : Automatic calibration memory enable setting for device 1
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ACMODE : Automatic calibration mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : 00
Automatic calibration is disabled
#01 : 01
Automatic calibration is enabled and modify MDTR
#10 : 10
Automatic calibration immediately is executed for all trim code, but it will not modify MDTR
#11 : 11
Setting prohibited
End of enumeration elements list.
DLFT : Deadlock Free Timer Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable timer
#1 : 1
Disable timer
End of enumeration elements list.
Memory Map Dummy Length Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DV0RDL : Device 0 Read dummy length setting
bits : 0 - 6 (7 bit)
access : read-write
DV0WDL : Device 0 Write dummy length setting
bits : 8 - 14 (7 bit)
access : read-write
DV1RDL : Device 1 Read dummy length setting
bits : 16 - 22 (7 bit)
access : read-write
DV1WDL : Device 1 Write dummy length setting
bits : 24 - 30 (7 bit)
access : read-write
Memory Map Read/Write Command Register 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0MRCMD0 : Memory map read command 0 setting
bits : 0 - 6 (7 bit)
access : read-write
D0MRCMD1 : Memory map read command 1 setting
bits : 8 - 14 (7 bit)
access : read-write
D0MWCMD0 : Memory map write command 0 setting
bits : 16 - 22 (7 bit)
access : read-write
D0MWCMD1 : Memory map write command 1 setting
bits : 24 - 30 (7 bit)
access : read-write
Memory Map Read/Write Command Register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D1MRCMD0 : Memory map read command 0 setting
bits : 0 - 6 (7 bit)
access : read-write
D1MRCMD1 : Memory map read command 1 setting
bits : 8 - 14 (7 bit)
access : read-write
D1MWCMD0 : Memory map write command 0 setting
bits : 16 - 22 (7 bit)
access : read-write
D1MWCMD1 : Memory map write command 1 setting
bits : 24 - 30 (7 bit)
access : read-write
Memory Map Read/Write Setting Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRAL0 : Device 0 read address length setting
bits : 0 - 1 (2 bit)
access : read-write
MRCL0 : Device 0 read command length setting
bits : 3 - 4 (2 bit)
access : read-write
MRO0 : Device 0 read order setting
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Read order is byte0, byte1, byte2, byte3.
#1 : 1
Read order is byte1, byte0, byte3, byte2.
End of enumeration elements list.
PREN0 : Preamble bit enable for mem0 memory-map read
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No check preamble bit
#1 : 1
Check preamble bit from OctaFlash (if OctaFlash is connected to device 0)
End of enumeration elements list.
MWAL0 : Device 0 write address length setting
bits : 8 - 9 (2 bit)
access : read-write
MWCL0 : Device 0 write command length setting
bits : 11 - 12 (2 bit)
access : read-write
MWO0 : Device 0 write order setting
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write order is byte0, byte1, byte2, byte3.
#1 : 1
Write order is byte1, byte0, byte3, byte2.
End of enumeration elements list.
MRAL1 : Device 1 read address length setting
bits : 16 - 17 (2 bit)
access : read-write
MRCL1 : Device 1 read command length setting
bits : 19 - 20 (2 bit)
access : read-write
MRO1 : Device 1 read order setting
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Read order is byte0, byte1, byte2, byte3.
#1 : 1
Read order is byte1, byte0, byte3, byte2.
End of enumeration elements list.
PREN1 : Preamble bit enable for mem1 memory-map read
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
No check preamble bit
#1 : 1
Check preamble bit from OctaFlash (if OctaFlash is connected to device 1)
End of enumeration elements list.
MWAL1 : Device 1 write address length setting
bits : 24 - 25 (2 bit)
access : read-write
MWCL1 : Device 1 write command length setting
bits : 27 - 28 (2 bit)
access : read-write
MWO1 : Device 1 write order setting
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write order is byte0, byte1, byte2, byte3.
#1 : 1
Write order is byte1, byte0, byte3, byte2.
End of enumeration elements list.
Error Status Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRESR : Memory map read error status
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x01 : 0x01
ECC error
0x02 : 0x02
Preamble error
0x03 : 0x03
Wait OM_DQS timeout
0x80 : 0x80
Invalid command
: Others
Reserved
End of enumeration elements list.
MWESR : Memory map write error status
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x80 : 0x80
Invalid command
: Others
Reserved
End of enumeration elements list.
Configure Write without Data Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WND : The write value should be 0.
bits : 0 - 30 (31 bit)
access : write-only
Configure Write Data Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WD0 : Write data 0
bits : 0 - 6 (7 bit)
access : write-only
WD1 : Write data 1
bits : 8 - 14 (7 bit)
access : write-only
WD2 : Write data 2
bits : 16 - 22 (7 bit)
access : write-only
WD3 : Write data 3
bits : 24 - 30 (7 bit)
access : write-only
Configure Read Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD0 : Read data 0
bits : 0 - 6 (7 bit)
access : read-only
RD1 : Read data 1
bits : 8 - 14 (7 bit)
access : read-only
RD2 : Read data 2
bits : 16 - 22 (7 bit)
access : read-only
RD3 : Read data 3
bits : 24 - 30 (7 bit)
access : read-only
Auto-Calibration Status Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACSR0 : Auto-calibration status of device 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
Initial state
#001 : 001
Reserved
#010 : 010
Reserved
#011 : 011
Normal end
#100 : 100
Error end
End of enumeration elements list.
ACSR1 : Auto-calibration status of device 1
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#000 : 000
Initial state
#001 : 001
Reserved
#010 : 010
Reserved
#011 : 011
Normal end
#100 : 100
Error end
End of enumeration elements list.
Device Chip Select Maximum Period Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTWMX0 : Indicates the maximum period that OM_CS0 and OM_CS1 are Low in single continuous write of OctaRAM.
bits : 0 - 7 (8 bit)
access : read-write
CTWMX1 : Indicates the maximum period that OM_CS0 and OM_CS1 are Low in single continuous read of OctaRAM.
bits : 16 - 23 (8 bit)
access : read-write
Device Command Setting Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DALEN : Transfer data length setting
bits : 0 - 6 (7 bit)
access : read-write
DMLEN : Dummy cycle setting
bits : 8 - 14 (7 bit)
access : read-write
ACDV : Access Device setting
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Send commands to device 0.
#1 : 1
Send commands to device 1.
End of enumeration elements list.
CMDLEN : Transfer command length setting
bits : 20 - 21 (2 bit)
access : read-write
DAOR : Data order setting
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
byte0, byte1, byte2, byte3
#1 : 1
byte1, byte0, byte3, byte2
End of enumeration elements list.
ADLEN : Transfer address length setting
bits : 24 - 25 (2 bit)
access : read-write
DOPI : DOPI single byte setting
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Each cycle has two bytes data. (normal DOPI mode)
#1 : 1
Each cycle has one byte data. (The byte data changes at the rising edge of the clock and does not change at the falling edge of the clock.)
End of enumeration elements list.
ACDA : Data Access Control
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Register access Do not arrange the transfer data.
#1 : 1
Data access
End of enumeration elements list.
PREN : Preamble bit enable for OctaRAM
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
No check preamble bit from OctaRAM
#1 : 1
Check preamble bit from OctaRAM
End of enumeration elements list.
Device Memory Map Write single continuous translating size Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTSN0 : Indicates the number of bytes to translate in single continuous write of device 0.
bits : 0 - 9 (10 bit)
access : read-write
CTSN1 : Indicates the number of bytes to translate in single continuous write of device 1.
bits : 16 - 25 (10 bit)
access : read-write
Device Size Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DV0SZ : Device 0 size setting
bits : 0 - 28 (29 bit)
access : read-write
DV0TYP : Device 0 type setting
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
flash on device 0
#01 : 01
RAM on device 0
#10 : 10
no connection on device 0
#11 : 11
forbidden
End of enumeration elements list.
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