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CEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4 Bytes (0x0)
size : 0x22 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x28 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x2A Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection :

Registers

CADR

STATLL

STATLH

STATBL

STATBH

LGC0LL

LGC0LH

LGC1LL

LGC1LH

CECCTL1

DATBL

DATBH

NOMP

CECEXMD

CECEXMON

STATB

CTXD

CRXD

CECES

CECS

CECFC

CECCTL0

STATL

LGC0L

LGC1L

DATB

CECINTCR1

CECINTCR2

NOMT

CECINTCR3


CADR

CEC Local Address Setting Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CADR CADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR00 ADR01 ADR02 ADR03 ADR04 ADR05 ADR06 ADR07 ADR08 ADR09 ADR10 ADR11 ADR12 ADR13 ADR14

ADR00 : Local Address at Address 0 (TV)
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR01 : Local Address Setting at Address 1 (recording device 1)
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR02 : Local Address Setting at Address 2 (recording device 2)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR03 : Local Address Setting at Address 3 (tuner 1)
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR04 : Local Address Setting at Address 4 (playback device 1)
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR05 : Local Address Setting at Address 5 (audio system)
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR06 : Local Address Setting at Address 6 (tuner 2)
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR07 : Local Address Setting at Address 7 (tuner 3)
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR08 : Local Address Setting at Address 8 (playback device 2)
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR09 : Local Address Setting at Address 9 (recording device 3)
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR10 : Local Address Setting at Address 10 (tuner 4)
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR11 : Local Address Setting at Address 11 (playback device 3)
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR12 : Local Address Setting at Address 12 (reserved)
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR13 : Local Address Setting at Address 13 (reserved)
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.

ADR14 : Local Address Setting at Address 14 (specific use)
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not set as local address.

#1 : 1

Sets as local address.

End of enumeration elements list.


STATLL

CEC Reception Start Bit Minimum Low Width Setting Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATLL STATLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATLL

STATLL : CEC Reception Start Bit Minimum Low Width Setting
bits : 0 - 7 (8 bit)
access : read-write


STATLH

CEC Reception Start Bit Maximum Low Width Setting Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATLH STATLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATLH

STATLH : CEC Reception Start Bit Maximum Bit Width Setting
bits : 0 - 7 (8 bit)
access : read-write


STATBL

CEC Reception Start Bit Minimum Bit Width Setting Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATBL STATBL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATBL

STATBL : CEC Reception Start Bit Minimum Bit Width Setting
bits : 0 - 7 (8 bit)
access : read-write


STATBH

CEC Reception Start Bit Maximum Bit Width Setting Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATBH STATBH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATBH

STATBH : CEC Reception Start Bit Maximum Bit Width Setting
bits : 0 - 7 (8 bit)
access : read-write


LGC0LL

CEC Reception Logical 0 Minimum Low Width Setting Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LGC0LL LGC0LL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGC0LL

LGC0LL : CEC Reception Logical 0 Minimum Low Width Setting
bits : 0 - 7 (8 bit)
access : read-write


LGC0LH

CEC Reception Logical 0 Maximum Low Width Setting Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LGC0LH LGC0LH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGC0LH

LGC0LH : CEC Reception Logical 0 Minimum Low Width Setting
bits : 0 - 7 (8 bit)
access : read-write


LGC1LL

CEC Reception Logical 1 Minimum Low Width Setting Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LGC1LL LGC1LL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGC1LL

LGC1LL : CEC Reception Logical 1 Minimum Low Width Setting
bits : 0 - 7 (8 bit)
access : read-write


LGC1LH

CEC Reception Logical 1 Maximum Low Width Setting Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LGC1LH LGC1LH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGC1LH

LGC1LH : CEC Reception Logical 1 Maximum Low Width Setting
bits : 0 - 7 (8 bit)
access : read-write


CECCTL1

CEC Control Register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECCTL1 CECCTL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SFT CESEL STERRD BLERRD CINTMK CDFC

SFT : Signal-Free Time Data Bit Width Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

3-data bit width

#01 : 01

5-data bit width

#10 : 10

7-data bit width

#11 : 11

Does not detect signal-free time.

End of enumeration elements list.

CESEL : Communication Complete Interrupt (INTCE) Generation Timing Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

Generates communication complete interrupt once after ACK transmission (reception) of the last frame (EOM = 1) is complete and another time after signal-free time is detected.

#01 : 01

Generates communication complete interrupt after ACK transmission (reception) of the last frame (EOM = 1) is completed.

#10 : 10

Generates communication complete interrupt after signal-free time is detected.

#11 : 11

Setting prohibited

End of enumeration elements list.

STERRD : Start Bit Error Detection Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not detect timing errors during start bit reception.

#1 : 1

Detects timing errors during start bit reception.

End of enumeration elements list.

BLERRD : Bus Lock Detection Select
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not detect sticking of receive data to high or low

#1 : 1

Detects sticking of receive data to high or low.

End of enumeration elements list.

CINTMK : CEC Data Interrupt (INTDA) Generation Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not generate an interrupt when the addresses do not match.

#1 : 1

Generates an interrupt when the addresses do not match.

End of enumeration elements list.

CDFC : Digital Filter Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not use a digital filter.

#1 : 1

Uses a digital filter.

End of enumeration elements list.


DATBL

CEC Reception Data Bit Minimum Bit Width Setting Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATBL DATBL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATBL

DATBL : CEC Reception Data Bit Minimum Bit Width Setting
bits : 0 - 7 (8 bit)
access : read-write


DATBH

CEC Reception Data Bit Maximum Bit Width Setting Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATBH DATBH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATBH

DATBH : CEC Reception Data Bit Maximum Bit Width Setting
bits : 0 - 7 (8 bit)
access : read-write


NOMP

CEC Data Bit Reference Width Setting Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NOMP NOMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOMP

NOMP : CEC Data Bit Reference Width Setting
bits : 0 - 7 (8 bit)
access : read-write


CECEXMD

CEC Extension Mode Register
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECEXMD CECEXMD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LERPLEN RERCVEN RCVINTDSEL

LERPLEN : Pulse Output Function Enable by Long Bit Width Error
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Detects only a long bit width error.

#1 : 1

Detects a long bit width error and outputs an error handling pulse.

End of enumeration elements list.

RERCVEN : Start Detection Reception Restart Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not restart reception when the start bit is detected during reception.

#1 : 1

Restarts reception when the start bit is detected during reception.

End of enumeration elements list.

RCVINTDSEL : INTDA Reception Interrupt Timing Change
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

EOM timing (9th bit of data)

#1 : 1

ACK timing (10th bit of data)

End of enumeration elements list.


CECEXMON

CEC Extension Monitor Register
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECEXMON CECEXMON read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CECLNMON ACKF

CECLNMON : CEC Line Monitor
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Low level

#1 : 1

High level

End of enumeration elements list.

ACKF : ACK Flag
bits : 1 - 0 (0 bit)
access : read-only


STATB

CEC Transmission Start Bit Width Setting Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATB STATB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATB

STATB : CEC Transmission Start Bit Width Setting
bits : 0 - 7 (8 bit)
access : read-write


CTXD

CEC Transmission Buffer Register
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXD CTXD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CRXD

CEC Reception Buffer Register
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRXD CRXD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CECES

CEC Communication Error Status Register
address_offset : 0x42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECES CECES read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OERR UERR ACKERR TERR TXERR AERR BLERR

OERR : Overrun Error Detection Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No overrun error has occurred.

#1 : 1

An overrun error has occurred.

End of enumeration elements list.

UERR : Underrun Error Detection Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No underrun error has occurred.

#1 : 1

An underrun error has occurred.

End of enumeration elements list.

ACKERR : ACK Error Detection Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No ACK error has occurred.

#1 : 1

An ACK error has occurred.

End of enumeration elements list.

TERR : Timing Error Detection Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

No timing error has occurred.

#1 : 1

A timing error has occurred.

End of enumeration elements list.

TXERR : Transmission Error Detection Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No transmission error has occurred.

#1 : 1

A transmission error has occurred.

End of enumeration elements list.

AERR : Arbitration Loss Detection Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

No arbitration loss has occurred.

#1 : 1

An arbitration loss has occurred.

End of enumeration elements list.

BLERR : Bus Lock Error Detection Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus lock error has occurred.

#1 : 1

A bus lock error has occurred.

End of enumeration elements list.


CECS

CEC Communication Status Register
address_offset : 0x43 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECS CECS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADRF BUSST TXST EOMF ITCEF SFTST

ADRF : Address Match Detection Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

During communication between other stations, while communication is stopped, or while the local station is transmitting

#1 : 1

During local reception

End of enumeration elements list.

BUSST : Bus Busy Detection Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Bus-free state

#1 : 1

Bus-busy state

End of enumeration elements list.

TXST : Transmission Status Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

During communication standby state or reception (a follower is operating.)

#1 : 1

During transmission (an initiator is operating.)

End of enumeration elements list.

EOMF : EOM Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

The EOM flag received immediately before is logically 0.

#1 : 1

The EOM flag received immediately before is logically 1.

End of enumeration elements list.

ITCEF : INTCE Generation Source Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Generates a communication complete interrupt (INTCE) if the signal-free time is counted.

#1 : 1

Generates INTCE if communication is complete or an error is detected.

End of enumeration elements list.

SFTST : Signal-Free Time Rewrite Disable Report Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

Enables rewriting CECCTL1.SFT[1:0].

#1 : 1

Disables rewriting CECCTL1.SFT[1:0].

End of enumeration elements list.


CECFC

CEC Communication Error Flag Clear Trigger Register
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECFC CECFC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OCTRG UCTRG ACKCTRG TCTRG TXCTRG ACTRG BLCTRG

OCTRG : Overrun Error Detection Flag Clear Trigger
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : 0

Does not clear overrun error detection flag.

#1 : 1

Clears overrun error detection flag.

End of enumeration elements list.

UCTRG : Underrun Error Detection Flag Clear Trigger
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : 0

Does not clear underrun error detection flag.

#1 : 1

Clears underrun error detection flag.

End of enumeration elements list.

ACKCTRG : ACK Error Detection Flag Clear Trigger
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : 0

Does not clear ACK error detection flag.

#1 : 1

Clears ACK error detection flag.

End of enumeration elements list.

TCTRG : Timing Error Detection Flag Clear Trigger
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : 0

Does not clear timing error detection flag.

#1 : 1

Clears timing error detection flag.

End of enumeration elements list.

TXCTRG : Transmission Error Detection Flag Clear Trigger
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : 0

Does not clear transmission error detection flag.

#1 : 1

Clears transmission error detection flag.

End of enumeration elements list.

ACTRG : Arbitration Loss Detection Flag Clear Trigger
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : 0

Does not clear arbitration loss detection flag.

#1 : 1

Clears arbitration loss detection flag.

End of enumeration elements list.

BLCTRG : Bus Lock Error Detection Flag Clear Trigger
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : 0

Does not clear bus lock error detection flag.

#1 : 1

Clears bus lock error detection flag.

End of enumeration elements list.


CECCTL0

CEC Control Register 0
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECCTL0 CECCTL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EOM CECRXEN TXTRG CCL ACKTEN CECE

EOM : EOM Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Continues transmission.

#1 : 1

Last frame

End of enumeration elements list.

CECRXEN : Reception Enable Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables continuing reception or reports abnormal reception.

#1 : 1

Enables continuing reception or reports normal reception. lists the reception status and ACK/NACK timing output.

End of enumeration elements list.

TXTRG : Transmission Start Trigger
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : 0

No effect

#1 : 1

Starts CEC transmission.

End of enumeration elements list.

CCL : CEC Clock (CECCLK) Select
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

#000 : 000

PCLKB/25

#001 : 001

PCLKB/26

#010 : 010

PCLKB/27

#011 : 011

PCLKB/28

#100 : 100

PCLKB/29

#101 : 101

PCLKB/210

#110 : 110

CECCLK (when using SOSC)

#111 : 111

CECCLK/28 (when using MOSC)

End of enumeration elements list.

ACKTEN : ACK Bit Timing Error (Bit Width) Check Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not detect ACK bit timing errors.

#1 : 1

Detects ACK bit timing errors.

End of enumeration elements list.

CECE : CEC Operation Enable Flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables CEC operation.

#1 : 1

Enables CEC operation.

End of enumeration elements list.


STATL

CEC Transmission Start Bit Low Width Setting Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATL STATL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATL

STATL : CEC Transmission Start Bit Low Width Setting
bits : 0 - 7 (8 bit)
access : read-write


LGC0L

CEC Transmission Logical 0 Low Width Setting Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LGC0L LGC0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGC0L

LGC0L : CEC Transmission Logical 0 Low Width Setting
bits : 0 - 7 (8 bit)
access : read-write


LGC1L

CEC Transmission Logical 1 Low Width Setting Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LGC1L LGC1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGC1L

LGC1L : CEC Transmission Logical 1 Low Width Setting
bits : 0 - 7 (8 bit)
access : read-write


DATB

CEC Transmission Data Bit Width Setting Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATB DATB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATB

DATB : CEC Transmission Data Bit Width Setting
bits : 0 - 7 (8 bit)
access : read-write


CECINTCR1

CEC Interrupt Control Register %s
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECINTCR1 CECINTCR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CECINTMD

CECINTMD : CEC Interrupt Detection Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

Low level

#01 : 01

Falling edge

#10 : 10

Rising edge

#11 : 11

Both edges

End of enumeration elements list.


CECINTCR2

CEC Interrupt Control Register %s
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECINTCR2 CECINTCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CECINTMD

CECINTMD : CEC Interrupt Detection Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

Low level

#01 : 01

Falling edge

#10 : 10

Rising edge

#11 : 11

Both edges

End of enumeration elements list.


NOMT

CEC Reception Data Sampling Time Setting Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NOMT NOMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOMT

NOMT : CEC Reception Data Sampling Time Setting,
bits : 0 - 7 (8 bit)
access : read-write


CECINTCR3

CEC Interrupt Control Register %s
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CECINTCR3 CECINTCR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CECINTMD

CECINTMD : CEC Interrupt Detection Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

Low level

#01 : 01

Falling edge

#10 : 10

Rising edge

#11 : 11

Both edges

End of enumeration elements list.



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