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Channel %s Nominal Bitrate Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NBRP : Channel Nominal Baud Rate Prescaler
bits : 0 - 8 (9 bit)
access : read-write
NSJW : Resynchronization Jump Width
bits : 10 - 15 (6 bit)
access : read-write
NTSEG1 : Timing Segment 1
bits : 17 - 23 (7 bit)
access : read-write
NTSEG2 : Timing Segment 2
bits : 25 - 30 (6 bit)
access : read-write
Channel %s Nominal Bitrate Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NBRP : Channel Nominal Baud Rate Prescaler
bits : 0 - 8 (9 bit)
access : read-write
NSJW : Resynchronization Jump Width
bits : 10 - 15 (6 bit)
access : read-write
NTSEG1 : Timing Segment 1
bits : 17 - 23 (7 bit)
access : read-write
NTSEG2 : Timing Segment 2
bits : 25 - 30 (6 bit)
access : read-write
RX FIFO Pointer Control Registers %s
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFPC : RX FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Configuration / Control Registers 0%s
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQE : TX Queue Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue disabled
#1 : 1
TX Queue enabled
End of enumeration elements list.
TXQGWE : TX Queue Gateway Mode Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue GW mode disabled
#1 : 1
TX Queue GW mode enabled
End of enumeration elements list.
TXQTXIE : TX Queue TX Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue TX Interrupt disabled
#1 : 1
TX Queue TX Interrupt enabled
End of enumeration elements list.
TXQIM : TX Queue Interrupt Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the last message is successfully transmitted
#1 : 1
At every successful transmission
End of enumeration elements list.
TXQDC : TX Queue Depth Configuration
bits : 8 - 11 (4 bit)
access : read-write
TXQFIE : TXQ Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue Full Interrupt generation disabled
#1 : 1
TX Queue Full Interrupt generation enabled
End of enumeration elements list.
TXQOFRXIE : TXQ One Frame Reception Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
TXQOFTXIE : TXQ One Frame Transmission Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
TX Queue Configuration / Control Registers 0%s
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQE : TX Queue Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue disabled
#1 : 1
TX Queue enabled
End of enumeration elements list.
TXQGWE : TX Queue Gateway Mode Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue GW mode disabled
#1 : 1
TX Queue GW mode enabled
End of enumeration elements list.
TXQTXIE : TX Queue TX Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue TX Interrupt disabled
#1 : 1
TX Queue TX Interrupt enabled
End of enumeration elements list.
TXQIM : TX Queue Interrupt Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the last message is successfully transmitted
#1 : 1
At every successful transmission
End of enumeration elements list.
TXQDC : TX Queue Depth Configuration
bits : 8 - 11 (4 bit)
access : read-write
TXQFIE : TXQ Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue Full Interrupt generation disabled
#1 : 1
TX Queue Full Interrupt generation enabled
End of enumeration elements list.
TXQOFRXIE : TXQ One Frame Reception Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
TXQOFTXIE : TXQ One Frame Transmission Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
TX Queue Status Registers 0%s
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQEMP : TX Queue Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Empty
#1 : 1
TX Queue Empty
End of enumeration elements list.
TXQFLL : TX Queue Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Full
#1 : 1
TX Queue Full
End of enumeration elements list.
TXQTXIF : TX Queue TX Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue interrupt condition not satisfied after Frame TX
#1 : 1
TX Queue interrupt condition satisfied after Frame TX
End of enumeration elements list.
TXQMC : TX Queue Message Count
bits : 8 - 12 (5 bit)
access : read-only
TXQFIF : TXQ Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
TXQOFRXIF : TXQ One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
TXQOFTXIF : TXQ One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
TXQMLT : TXQ Message Lost
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in TXQ
#1 : 1
TXQ Message Lost
End of enumeration elements list.
TX Queue Status Registers 0%s
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQEMP : TX Queue Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Empty
#1 : 1
TX Queue Empty
End of enumeration elements list.
TXQFLL : TX Queue Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Full
#1 : 1
TX Queue Full
End of enumeration elements list.
TXQTXIF : TX Queue TX Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue interrupt condition not satisfied after Frame TX
#1 : 1
TX Queue interrupt condition satisfied after Frame TX
End of enumeration elements list.
TXQMC : TX Queue Message Count
bits : 8 - 12 (5 bit)
access : read-only
TXQFIF : TXQ Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
TXQOFRXIF : TXQ One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
TXQOFTXIF : TXQ One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
TXQMLT : TXQ Message Lost
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in TXQ
#1 : 1
TXQ Message Lost
End of enumeration elements list.
RX FIFO Pointer Control Registers %s
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFPC : RX FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Pointer Control Registers 0%s
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQPC : TX Queue Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Pointer Control Registers 0%s
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQPC : TX Queue Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Configuration / Control Registers 1%s
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQE : TX Queue Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue disabled
#1 : 1
TX Queue enabled
End of enumeration elements list.
TXQGWE : TX Queue Gateway Mode Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue GW mode disabled
#1 : 1
TX Queue GW mode enabled
End of enumeration elements list.
TXQTXIE : TX Queue TX Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue TX Interrupt disabled
#1 : 1
TX Queue TX Interrupt enabled
End of enumeration elements list.
TXQIM : TX Queue Interrupt Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the last message is successfully transmitted
#1 : 1
At every successful transmission
End of enumeration elements list.
TXQDC : TX Queue Depth Configuration
bits : 8 - 11 (4 bit)
access : read-write
TXQFIE : TXQ Full Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue Full Interrupt generation disabled
#1 : 1
TX Queue Full Interrupt generation enabled
End of enumeration elements list.
TXQOFRXIE : TXQ One Frame Reception Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
TXQOFTXIE : TXQ One Frame Transmission Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
TX Queue Configuration / Control Registers 1%s
address_offset : 0x1064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQE : TX Queue Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue disabled
#1 : 1
TX Queue enabled
End of enumeration elements list.
TXQGWE : TX Queue Gateway Mode Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue GW mode disabled
#1 : 1
TX Queue GW mode enabled
End of enumeration elements list.
TXQTXIE : TX Queue TX Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue TX Interrupt disabled
#1 : 1
TX Queue TX Interrupt enabled
End of enumeration elements list.
TXQIM : TX Queue Interrupt Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the last message is successfully transmitted
#1 : 1
At every successful transmission
End of enumeration elements list.
TXQDC : TX Queue Depth Configuration
bits : 8 - 11 (4 bit)
access : read-write
TXQFIE : TXQ Full Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue Full Interrupt generation disabled
#1 : 1
TX Queue Full Interrupt generation enabled
End of enumeration elements list.
TXQOFRXIE : TXQ One Frame Reception Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
TXQOFTXIE : TXQ One Frame Transmission Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
RX FIFO Pointer Control Registers %s
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFPC : RX FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Status Registers 1%s
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQEMP : TX Queue Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Empty
#1 : 1
TX Queue Empty
End of enumeration elements list.
TXQFLL : TX Queue Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Full
#1 : 1
TX Queue Full
End of enumeration elements list.
TXQTXIF : TX Queue TX Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue interrupt condition not satisfied after Frame TX
#1 : 1
TX Queue interrupt condition satisfied after Frame TX
End of enumeration elements list.
TXQMC : TX Queue Message Count
bits : 8 - 12 (5 bit)
access : read-only
TXQFIF : TXQ Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
TXQOFRXIF : TXQ One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
TXQOFTXIF : TXQ One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
TXQMLT : TXQ Message Lost
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in TXQ
#1 : 1
TXQ Message Lost
End of enumeration elements list.
TX Queue Status Registers 1%s
address_offset : 0x1084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQEMP : TX Queue Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Empty
#1 : 1
TX Queue Empty
End of enumeration elements list.
TXQFLL : TX Queue Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Full
#1 : 1
TX Queue Full
End of enumeration elements list.
TXQTXIF : TX Queue TX Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue interrupt condition not satisfied after Frame TX
#1 : 1
TX Queue interrupt condition satisfied after Frame TX
End of enumeration elements list.
TXQMC : TX Queue Message Count
bits : 8 - 12 (5 bit)
access : read-only
TXQFIF : TXQ Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
TXQOFRXIF : TXQ One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
TXQOFTXIF : TXQ One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
TXQMLT : TXQ Message Lost
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in TXQ
#1 : 1
TXQ Message Lost
End of enumeration elements list.
TX Queue Pointer Control Registers 1%s
address_offset : 0x10A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQPC : TX Queue Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Pointer Control Registers 1%s
address_offset : 0x10A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQPC : TX Queue Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
RX FIFO Pointer Control Registers %s
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFPC : RX FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Configuration / Control Registers 2%s
address_offset : 0x10C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQE : TX Queue Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue disabled
#1 : 1
TX Queue enabled
End of enumeration elements list.
TXQGWE : TX Queue Gateway Mode Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue GW mode disabled
#1 : 1
TX Queue GW mode enabled
End of enumeration elements list.
TXQTXIE : TX Queue TX Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue TX Interrupt disabled
#1 : 1
TX Queue TX Interrupt enabled
End of enumeration elements list.
TXQIM : TX Queue Interrupt Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the last message is successfully transmitted
#1 : 1
At every successful transmission
End of enumeration elements list.
TXQDC : TX Queue Depth Configuration
bits : 8 - 11 (4 bit)
access : read-write
TXQFIE : TXQ Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue Full Interrupt generation disabled
#1 : 1
TX Queue Full Interrupt generation enabled
End of enumeration elements list.
TXQOFRXIE : TXQ One Frame Reception Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
TXQOFTXIE : TXQ One Frame Transmission Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
TX Queue Configuration / Control Registers 2%s
address_offset : 0x10C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQE : TX Queue Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue disabled
#1 : 1
TX Queue enabled
End of enumeration elements list.
TXQGWE : TX Queue Gateway Mode Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue GW mode disabled
#1 : 1
TX Queue GW mode enabled
End of enumeration elements list.
TXQTXIE : TX Queue TX Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue TX Interrupt disabled
#1 : 1
TX Queue TX Interrupt enabled
End of enumeration elements list.
TXQIM : TX Queue Interrupt Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the last message is successfully transmitted
#1 : 1
At every successful transmission
End of enumeration elements list.
TXQDC : TX Queue Depth Configuration
bits : 8 - 11 (4 bit)
access : read-write
TXQFIE : TXQ Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue Full Interrupt generation disabled
#1 : 1
TX Queue Full Interrupt generation enabled
End of enumeration elements list.
TXQOFRXIE : TXQ One Frame Reception Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
TXQOFTXIE : TXQ One Frame Transmission Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
TX Queue Status Registers 2%s
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQEMP : TX Queue Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Empty
#1 : 1
TX Queue Empty
End of enumeration elements list.
TXQFLL : TX Queue Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Full
#1 : 1
TX Queue Full
End of enumeration elements list.
TXQTXIF : TX Queue TX Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue interrupt condition not satisfied after Frame TX
#1 : 1
TX Queue interrupt condition satisfied after Frame TX
End of enumeration elements list.
TXQMC : TX Queue Message Count
bits : 8 - 12 (5 bit)
access : read-only
TXQFIF : TXQ Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
TXQOFRXIF : TXQ One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
TXQOFTXIF : TXQ One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
TXQMLT : TXQ Message Lost
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in TXQ
#1 : 1
TXQ Message Lost
End of enumeration elements list.
TX Queue Status Registers 2%s
address_offset : 0x10E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQEMP : TX Queue Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Empty
#1 : 1
TX Queue Empty
End of enumeration elements list.
TXQFLL : TX Queue Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Full
#1 : 1
TX Queue Full
End of enumeration elements list.
TXQTXIF : TX Queue TX Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue interrupt condition not satisfied after Frame TX
#1 : 1
TX Queue interrupt condition satisfied after Frame TX
End of enumeration elements list.
TXQMC : TX Queue Message Count
bits : 8 - 12 (5 bit)
access : read-only
TXQFIF : TXQ Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
TXQOFRXIF : TXQ One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
TXQOFTXIF : TXQ One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
TXQMLT : TXQ Message Lost
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in TXQ
#1 : 1
TXQ Message Lost
End of enumeration elements list.
RX FIFO Pointer Control Registers %s
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFPC : RX FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Pointer Control Registers 2%s
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQPC : TX Queue Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Pointer Control Registers 2%s
address_offset : 0x1104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQPC : TX Queue Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Configuration / Control Registers 3%s
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQE : TX Queue Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue disabled
#1 : 1
TX Queue enabled
End of enumeration elements list.
TXQTXIE : TX Queue TX Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue TX Interrupt disabled
#1 : 1
TX Queue TX Interrupt enabled
End of enumeration elements list.
TXQIM : TX Queue Interrupt Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the last message is successfully transmitted
#1 : 1
At every successful transmission
End of enumeration elements list.
TXQDC : TX Queue Depth Configuration
bits : 8 - 11 (4 bit)
access : read-write
TXQOFTXIE : TXQ One Frame Transmission Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
TX Queue Configuration / Control Registers 3%s
address_offset : 0x1124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQE : TX Queue Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue disabled
#1 : 1
TX Queue enabled
End of enumeration elements list.
TXQTXIE : TX Queue TX Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue TX Interrupt disabled
#1 : 1
TX Queue TX Interrupt enabled
End of enumeration elements list.
TXQIM : TX Queue Interrupt Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the last message is successfully transmitted
#1 : 1
At every successful transmission
End of enumeration elements list.
TXQDC : TX Queue Depth Configuration
bits : 8 - 11 (4 bit)
access : read-write
TXQOFTXIE : TXQ One Frame Transmission Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
RX FIFO Pointer Control Registers %s
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFPC : RX FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Status Registers 3%s
address_offset : 0x1140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQEMP : TX Queue Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Empty
#1 : 1
TX Queue Empty
End of enumeration elements list.
TXQFLL : TX Queue Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Full
#1 : 1
TX Queue Full
End of enumeration elements list.
TXQTXIF : TX Queue TX Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue interrupt condition not satisfied after Frame TX
#1 : 1
TX Queue interrupt condition satisfied after Frame TX
End of enumeration elements list.
TXQMC : TX Queue Message Count
bits : 8 - 12 (5 bit)
access : read-only
TXQOFTXIF : TXQ One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
TX Queue Status Registers 3%s
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQEMP : TX Queue Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Empty
#1 : 1
TX Queue Empty
End of enumeration elements list.
TXQFLL : TX Queue Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Queue Not Full
#1 : 1
TX Queue Full
End of enumeration elements list.
TXQTXIF : TX Queue TX Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Queue interrupt condition not satisfied after Frame TX
#1 : 1
TX Queue interrupt condition satisfied after Frame TX
End of enumeration elements list.
TXQMC : TX Queue Message Count
bits : 8 - 12 (5 bit)
access : read-only
TXQOFTXIF : TXQ One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
TX Queue Pointer Control Registers 3%s
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQPC : TX Queue Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Pointer Control Registers 3%s
address_offset : 0x1164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQPC : TX Queue Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
RX FIFO Pointer Control Registers %s
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFPC : RX FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX Queue Empty Status Register
address_offset : 0x1180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXQxEMP : TXQ empty Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
TXQ not empty
#1 : 1
TXQ empty
End of enumeration elements list.
TX Queue Full Interrupt Status Register
address_offset : 0x1184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQ0FULL : TXQ Full Interrupt Status for channel 0
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#0 : 0
TXQ Full Interrupt is not set
#1 : 1
TXQ Full Interrupt is set
End of enumeration elements list.
TXQ1FULL : TXQ Full Interrupt Status for channel 1
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#0 : 0
TXQ Full Interrupt is not set
#1 : 1
TXQ Full Interrupt is set
End of enumeration elements list.
TX Queue Message Lost Status Register
address_offset : 0x1188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQ0ML : TXQ message lost Status for channel 0
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#0 : 0
TXQ message lost flag is not set
#1 : 1
TXQ message lost flag is set
End of enumeration elements list.
TXQ1ML : TXQ message lost Status for channel 1
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#0 : 0
TXQ message lost flag is not set
#1 : 1
TXQ message lost flag is set
End of enumeration elements list.
TX Queue Interrupt Status Register
address_offset : 0x1190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQ0ISF : TXQ Interrupt Status Flag for channel 0
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#0 : 0
TXQ Interrupt flag is not set
#1 : 1
TXQ Interrupt flag is set
End of enumeration elements list.
TXQ1ISF : TXQ Interrupt Status Flag for channel 1
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#0 : 0
TXQ Interrupt flag is not set
#1 : 1
TXQ Interrupt flag is set
End of enumeration elements list.
TX Queue One Frame TX Interrupt Status Register
address_offset : 0x1194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQ0OFTISF : TXQ One Frame TX Interrupt Status Flag for channel 0
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#0 : 0
TXQ One Frame TX Interrupt flag is not set
#1 : 1
TXQ One Frame TX Interrupt flag is set
End of enumeration elements list.
TXQ1OFTISF : TXQ One Frame TX Interrupt Status Flag for channel 1
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#0 : 0
TXQ One Frame TX Interrupt flag is not set
#1 : 1
TXQ One Frame TX Interrupt flag is set
End of enumeration elements list.
TX Queue One Frame RX Interrupt Status Register
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXQ0OFRISF : TXQ One Frame RX Interrupt Status Flag
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#0 : 0
TXQ One Frame RX Interrupt flag is not set
#1 : 1
TXQ One Frame RX Interrupt flag is set
End of enumeration elements list.
TXQ1OFRISF : TXQ One Frame RX Interrupt Status Flag
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#0 : 0
TXQ One Frame RX Interrupt flag is not set
#1 : 1
TXQ One Frame RX Interrupt flag is set
End of enumeration elements list.
TX Queue Full Status Register
address_offset : 0x119C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXQ0FSF : TXQ Full Status Flag for channel 0
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#0 : 0
TXQ Full flag is not set
#1 : 1
TXQ Full flag is set
End of enumeration elements list.
TXQ1FSF : TXQ Full Status Flag for channel 1
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#0 : 0
TXQ Full flag is not set
#1 : 1
TXQ Full flag is set
End of enumeration elements list.
RX FIFO Pointer Control Registers %s
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFPC : RX FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
Common FIFO Configuration / Control Registers %s
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFE : Common FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
CFRXIE : Common FIFO RX Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame RX
#1 : 1
FIFO Interrupt generation enabled for Frame RX
End of enumeration elements list.
CFTXIE : Common FIFO TX Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame TX
#1 : 1
FIFO Interrupt generation enabled for Frame TX
End of enumeration elements list.
CFPLS : Common FIFO Payload Data size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bytes
#001 : 001
12 bytes
#010 : 010
16 bytes
#011 : 011
20 bytes
#100 : 100
24 bytes
#101 : 101
32 bytes
#110 : 110
48 bytes
#111 : 111
64 bytes
End of enumeration elements list.
CFM : Common FIFO Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
RX FIFO Mode
#01 : 01
TX FIFO Mode
#10 : 10
CAN – CAN GW FIFO Mode
#11 : 11
Reserved
End of enumeration elements list.
CFITSS : Common FIFO Interval Timer Source Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock (×1 / ×10 period)
#1 : 1
Bit Time Clock of related channel (FIFO is linked to fixed channel)
End of enumeration elements list.
CFITR : Common FIFO Interval Timer Resolution
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock Period ×1
#1 : 1
Reference Clock Period ×10
End of enumeration elements list.
CFIM : Common FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO Mode: RX Interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO Mode: TX Interrupt generated when Common FIFO transmits the last message successfully GW FIFO Mode: For RX interrupt flag: Interrupt generated when FIFO counter increments and reaches the value configured in CFIGCV For TX interrupt flag: Interrupt generated when FIFO transmits the last message successfully
#1 : 1
RX FIFO Mode: RX Interrupt generated at the end of every received message storage TX FIFO Mode: Interrupt generated for every successfully transmitted message GW FIFO Mode: For RX interrupt flag: Interrupt generated when a message is stored in the FIFO For TX interrupt flag: Interrupt generated when a message is successfully transmitted from the FIFO
End of enumeration elements list.
CFIGCV : Common FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
CFTML : Common FIFO TX Message Buffer Link
bits : 16 - 19 (4 bit)
access : read-write
CFDC : Common FIFO Depth Configuration
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
CFITT : Common FIFO Interval Transmission Time
bits : 24 - 30 (7 bit)
access : read-write
TX History List Configuration / Control Register %s
address_offset : 0x1200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THLE : TX History List Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX History List disabled
#1 : 1
TX History List enabled
End of enumeration elements list.
THLIE : TX History List Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX History List Interrupt disabled
#1 : 1
TX History List Interrupt enabled
End of enumeration elements list.
THLIM : TX History List Interrupt Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated if TX History List level reaches ¾ of the TX History List depth.
#1 : 1
Interrupt generated for every successfully stored entry
End of enumeration elements list.
THLDTE : TX History List Dedicated TX Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO + TX Queue
#1 : 1
Flat TX MB + TX FIFO + TX Queue
End of enumeration elements list.
THLDGE : TX History List Dedicated GW Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not dedicate Gateway FIFO + Gateway TX Queue
#1 : 1
Dedicate Gateway FIFO + Gateway TX Queue
End of enumeration elements list.
TX History List Configuration / Control Register %s
address_offset : 0x1204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THLE : TX History List Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX History List disabled
#1 : 1
TX History List enabled
End of enumeration elements list.
THLIE : TX History List Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX History List Interrupt disabled
#1 : 1
TX History List Interrupt enabled
End of enumeration elements list.
THLIM : TX History List Interrupt Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated if TX History List level reaches ¾ of the TX History List depth.
#1 : 1
Interrupt generated for every successfully stored entry
End of enumeration elements list.
THLDTE : TX History List Dedicated TX Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO + TX Queue
#1 : 1
Flat TX MB + TX FIFO + TX Queue
End of enumeration elements list.
THLDGE : TX History List Dedicated GW Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not dedicate Gateway FIFO + Gateway TX Queue
#1 : 1
Dedicate Gateway FIFO + Gateway TX Queue
End of enumeration elements list.
TX History List Status Register %s
address_offset : 0x1220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THLEMP : TX History List Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX History List Not Empty
#1 : 1
TX History List Empty
End of enumeration elements list.
THLFLL : TX History List Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX History List Not Full
#1 : 1
TX History List Full
End of enumeration elements list.
THLELT : TX History List Entry Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Entry Lost in TX History List
#1 : 1
TX History List Entry Lost
End of enumeration elements list.
THLIF : TX History List Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX History List Interrupt condition not satisfied
#1 : 1
TX History List Interrupt condition satisfied
End of enumeration elements list.
THLMC : TX History List Message Count
bits : 8 - 12 (5 bit)
access : read-only
TX History List Status Register %s
address_offset : 0x1224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THLEMP : TX History List Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX History List Not Empty
#1 : 1
TX History List Empty
End of enumeration elements list.
THLFLL : TX History List Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX History List Not Full
#1 : 1
TX History List Full
End of enumeration elements list.
THLELT : TX History List Entry Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Entry Lost in TX History List
#1 : 1
TX History List Entry Lost
End of enumeration elements list.
THLIF : TX History List Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX History List Interrupt condition not satisfied
#1 : 1
TX History List Interrupt condition satisfied
End of enumeration elements list.
THLMC : TX History List Message Count
bits : 8 - 12 (5 bit)
access : read-only
Common FIFO Configuration / Control Registers %s
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFE : Common FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
CFRXIE : Common FIFO RX Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame RX
#1 : 1
FIFO Interrupt generation enabled for Frame RX
End of enumeration elements list.
CFTXIE : Common FIFO TX Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame TX
#1 : 1
FIFO Interrupt generation enabled for Frame TX
End of enumeration elements list.
CFPLS : Common FIFO Payload Data size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bytes
#001 : 001
12 bytes
#010 : 010
16 bytes
#011 : 011
20 bytes
#100 : 100
24 bytes
#101 : 101
32 bytes
#110 : 110
48 bytes
#111 : 111
64 bytes
End of enumeration elements list.
CFM : Common FIFO Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
RX FIFO Mode
#01 : 01
TX FIFO Mode
#10 : 10
CAN – CAN GW FIFO Mode
#11 : 11
Reserved
End of enumeration elements list.
CFITSS : Common FIFO Interval Timer Source Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock (×1 / ×10 period)
#1 : 1
Bit Time Clock of related channel (FIFO is linked to fixed channel)
End of enumeration elements list.
CFITR : Common FIFO Interval Timer Resolution
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock Period ×1
#1 : 1
Reference Clock Period ×10
End of enumeration elements list.
CFIM : Common FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO Mode: RX Interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO Mode: TX Interrupt generated when Common FIFO transmits the last message successfully GW FIFO Mode: For RX interrupt flag: Interrupt generated when FIFO counter increments and reaches the value configured in CFIGCV For TX interrupt flag: Interrupt generated when FIFO transmits the last message successfully
#1 : 1
RX FIFO Mode: RX Interrupt generated at the end of every received message storage TX FIFO Mode: Interrupt generated for every successfully transmitted message GW FIFO Mode: For RX interrupt flag: Interrupt generated when a message is stored in the FIFO For TX interrupt flag: Interrupt generated when a message is successfully transmitted from the FIFO
End of enumeration elements list.
CFIGCV : Common FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
CFTML : Common FIFO TX Message Buffer Link
bits : 16 - 19 (4 bit)
access : read-write
CFDC : Common FIFO Depth Configuration
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
CFITT : Common FIFO Interval Transmission Time
bits : 24 - 30 (7 bit)
access : read-write
TX History List Pointer Control Registers %s
address_offset : 0x1240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THLPC : TX History List Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
TX History List Pointer Control Registers %s
address_offset : 0x1244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THLPC : TX History List Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
Common FIFO Configuration / Control Registers %s
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFE : Common FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
CFRXIE : Common FIFO RX Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame RX
#1 : 1
FIFO Interrupt generation enabled for Frame RX
End of enumeration elements list.
CFTXIE : Common FIFO TX Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame TX
#1 : 1
FIFO Interrupt generation enabled for Frame TX
End of enumeration elements list.
CFPLS : Common FIFO Payload Data size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bytes
#001 : 001
12 bytes
#010 : 010
16 bytes
#011 : 011
20 bytes
#100 : 100
24 bytes
#101 : 101
32 bytes
#110 : 110
48 bytes
#111 : 111
64 bytes
End of enumeration elements list.
CFM : Common FIFO Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
RX FIFO Mode
#01 : 01
TX FIFO Mode
#10 : 10
CAN – CAN GW FIFO Mode
#11 : 11
Reserved
End of enumeration elements list.
CFITSS : Common FIFO Interval Timer Source Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock (×1 / ×10 period)
#1 : 1
Bit Time Clock of related channel (FIFO is linked to fixed channel)
End of enumeration elements list.
CFITR : Common FIFO Interval Timer Resolution
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock Period ×1
#1 : 1
Reference Clock Period ×10
End of enumeration elements list.
CFIM : Common FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO Mode: RX Interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO Mode: TX Interrupt generated when Common FIFO transmits the last message successfully GW FIFO Mode: For RX interrupt flag: Interrupt generated when FIFO counter increments and reaches the value configured in CFIGCV For TX interrupt flag: Interrupt generated when FIFO transmits the last message successfully
#1 : 1
RX FIFO Mode: RX Interrupt generated at the end of every received message storage TX FIFO Mode: Interrupt generated for every successfully transmitted message GW FIFO Mode: For RX interrupt flag: Interrupt generated when a message is stored in the FIFO For TX interrupt flag: Interrupt generated when a message is successfully transmitted from the FIFO
End of enumeration elements list.
CFIGCV : Common FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
CFTML : Common FIFO TX Message Buffer Link
bits : 16 - 19 (4 bit)
access : read-write
CFDC : Common FIFO Depth Configuration
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
CFITT : Common FIFO Interval Transmission Time
bits : 24 - 30 (7 bit)
access : read-write
Common FIFO Configuration / Control Registers %s
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFE : Common FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
CFRXIE : Common FIFO RX Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame RX
#1 : 1
FIFO Interrupt generation enabled for Frame RX
End of enumeration elements list.
CFTXIE : Common FIFO TX Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame TX
#1 : 1
FIFO Interrupt generation enabled for Frame TX
End of enumeration elements list.
CFPLS : Common FIFO Payload Data size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bytes
#001 : 001
12 bytes
#010 : 010
16 bytes
#011 : 011
20 bytes
#100 : 100
24 bytes
#101 : 101
32 bytes
#110 : 110
48 bytes
#111 : 111
64 bytes
End of enumeration elements list.
CFM : Common FIFO Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
RX FIFO Mode
#01 : 01
TX FIFO Mode
#10 : 10
CAN – CAN GW FIFO Mode
#11 : 11
Reserved
End of enumeration elements list.
CFITSS : Common FIFO Interval Timer Source Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock (×1 / ×10 period)
#1 : 1
Bit Time Clock of related channel (FIFO is linked to fixed channel)
End of enumeration elements list.
CFITR : Common FIFO Interval Timer Resolution
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock Period ×1
#1 : 1
Reference Clock Period ×10
End of enumeration elements list.
CFIM : Common FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO Mode: RX Interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO Mode: TX Interrupt generated when Common FIFO transmits the last message successfully GW FIFO Mode: For RX interrupt flag: Interrupt generated when FIFO counter increments and reaches the value configured in CFIGCV For TX interrupt flag: Interrupt generated when FIFO transmits the last message successfully
#1 : 1
RX FIFO Mode: RX Interrupt generated at the end of every received message storage TX FIFO Mode: Interrupt generated for every successfully transmitted message GW FIFO Mode: For RX interrupt flag: Interrupt generated when a message is stored in the FIFO For TX interrupt flag: Interrupt generated when a message is successfully transmitted from the FIFO
End of enumeration elements list.
CFIGCV : Common FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
CFTML : Common FIFO TX Message Buffer Link
bits : 16 - 19 (4 bit)
access : read-write
CFDC : Common FIFO Depth Configuration
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
CFITT : Common FIFO Interval Transmission Time
bits : 24 - 30 (7 bit)
access : read-write
Common FIFO Configuration / Control Registers %s
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFE : Common FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
CFRXIE : Common FIFO RX Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame RX
#1 : 1
FIFO Interrupt generation enabled for Frame RX
End of enumeration elements list.
CFTXIE : Common FIFO TX Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame TX
#1 : 1
FIFO Interrupt generation enabled for Frame TX
End of enumeration elements list.
CFPLS : Common FIFO Payload Data size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bytes
#001 : 001
12 bytes
#010 : 010
16 bytes
#011 : 011
20 bytes
#100 : 100
24 bytes
#101 : 101
32 bytes
#110 : 110
48 bytes
#111 : 111
64 bytes
End of enumeration elements list.
CFM : Common FIFO Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
RX FIFO Mode
#01 : 01
TX FIFO Mode
#10 : 10
CAN – CAN GW FIFO Mode
#11 : 11
Reserved
End of enumeration elements list.
CFITSS : Common FIFO Interval Timer Source Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock (×1 / ×10 period)
#1 : 1
Bit Time Clock of related channel (FIFO is linked to fixed channel)
End of enumeration elements list.
CFITR : Common FIFO Interval Timer Resolution
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock Period ×1
#1 : 1
Reference Clock Period ×10
End of enumeration elements list.
CFIM : Common FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO Mode: RX Interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO Mode: TX Interrupt generated when Common FIFO transmits the last message successfully GW FIFO Mode: For RX interrupt flag: Interrupt generated when FIFO counter increments and reaches the value configured in CFIGCV For TX interrupt flag: Interrupt generated when FIFO transmits the last message successfully
#1 : 1
RX FIFO Mode: RX Interrupt generated at the end of every received message storage TX FIFO Mode: Interrupt generated for every successfully transmitted message GW FIFO Mode: For RX interrupt flag: Interrupt generated when a message is stored in the FIFO For TX interrupt flag: Interrupt generated when a message is successfully transmitted from the FIFO
End of enumeration elements list.
CFIGCV : Common FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
CFTML : Common FIFO TX Message Buffer Link
bits : 16 - 19 (4 bit)
access : read-write
CFDC : Common FIFO Depth Configuration
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
CFITT : Common FIFO Interval Transmission Time
bits : 24 - 30 (7 bit)
access : read-write
Global TX Interrupt Status Register 0
address_offset : 0x1300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSIF0 : TX Successful Interrupt Flag Channel 0
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX Successful completion Interrupt flag not set
#1 : 1
Channel n TX Successful completion Interrupt flag set
End of enumeration elements list.
TAIF0 : TX Abort Interrupt Flag Channel 0
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX abort Interrupt flag not set
#1 : 1
Channel n TX abort Interrupt flag set
End of enumeration elements list.
TQIF0 : TX Queue Interrupt Flag Channel 0
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX Queue Interrupt flag not set
#1 : 1
Channel n TX Queue Interrupt flag set
End of enumeration elements list.
CFTIF0 : COM FIFO TX/GW Mode Interrupt Flag Channel 0
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n COM FIFO TX/GW mode Interrupt flag not set
#1 : 1
Channel n COM FIFO TX/GW mode Interrupt flag set
End of enumeration elements list.
THIF0 : TX History List Interrupt Channel 0
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX History List Interrupt flag not set
#1 : 1
Channel n TX History List Interrupt flag set
End of enumeration elements list.
TQOFIF0 : TX Queue One Frame Transmission Interrupt Flag Channel 0
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX Queue One Frame Transmission Interrupt flag not set
#1 : 1
Channel n TX Queue One Frame Transmission Interrupt flag set
End of enumeration elements list.
CFOTIF0 : COM FIFO One Frame Transmission Interrupt Flag Channel 0
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n COM FIFO One Frame Transmission Interrupt flag not set
#1 : 1
Channel n COM FIFO One Frame Transmission Interrupt flag set
End of enumeration elements list.
TSIF1 : TX Successful Interrupt Flag Channel 1
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX Successful completion Interrupt flag not set
#1 : 1
Channel n TX Successful completion Interrupt flag set
End of enumeration elements list.
TAIF1 : TX Abort Interrupt Flag Channel 1
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX abort Interrupt flag not set
#1 : 1
Channel n TX abort Interrupt flag set
End of enumeration elements list.
TQIF1 : TX Queue Interrupt Flag Channel 1
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX Queue Interrupt flag not set
#1 : 1
Channel n TX Queue Interrupt flag set
End of enumeration elements list.
CFTIF1 : COM FIFO TX/GW Mode Interrupt Flag Channel 1
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n COM FIFO TX/GW mode Interrupt flag not set
#1 : 1
Channel n COM FIFO TX/GW mode Interrupt flag set
End of enumeration elements list.
THIF1 : TX History List Interrupt Channel 1
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX History List Interrupt flag not set
#1 : 1
Channel n TX History List Interrupt flag set
End of enumeration elements list.
TQOFIF1 : TX Queue One Frame Transmission Interrupt Flag Channel 1
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n TX Queue One Frame Transmission Interrupt flag not set
#1 : 1
Channel n TX Queue One Frame Transmission Interrupt flag set
End of enumeration elements list.
CFOTIF1 : COM FIFO One Frame Transmission Interrupt Flag Channel 1
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel n COM FIFO One Frame Transmission Interrupt flag not set
#1 : 1
Channel n COM FIFO One Frame Transmission Interrupt flag set
End of enumeration elements list.
Global Test Configuration Register
address_offset : 0x1308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICBCE : Channel n Internal CAN Bus Communication Test Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n internal CAN bus communication disabled
#1 : 1
Channel n internal CAN bus communication enabled
End of enumeration elements list.
RTMPS : RAM Test Mode Page Select
bits : 16 - 24 (9 bit)
access : read-write
Global Test Control Register
address_offset : 0x130C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICBCTME : Internal CAN Bus Communication Test Mode Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Internal CAN Bus communication test mode disabled
#1 : 1
Internal CAN Bus communication test mode enabled
End of enumeration elements list.
RTME : RAM Test Mode Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
RAM Test Mode disabled
#1 : 1
RAM Test Mode enabled
End of enumeration elements list.
Global FD Configuration register
address_offset : 0x1314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPED : RES bit Protocol exception disable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Protocol exception event detection enabled
#1 : 1
Protocol exception event detection disabled
End of enumeration elements list.
TSCCFG : Timestamp capture configuration
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
Timestamp capture at the sample point of SOF (start of frame)
#01 : 01
Timestamp capture at frame valid indication
#10 : 10
Timestamp capture at the sample point of RES bit
#11 : 11
reserved
End of enumeration elements list.
Global FD CRC Configuration register
address_offset : 0x1318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NIE : Non ISO enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
CAN FD frame format according to ISO 11898-1
#1 : 1
CAN FD frame format according to Bosch CAN FD Specification V1.0
End of enumeration elements list.
Global Lock Key Register
address_offset : 0x131C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : Lock Key
bits : 0 - 14 (15 bit)
access : write-only
Global OTB FIFO Configuration / Status Register
address_offset : 0x1320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTBFE : OTB FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
OTBEMP : OTB FIFO Empty
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
OTBFLL : OTB FIFO Full
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
OTBMLT : OTB FIFO Message Lost
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
OTBMC : OTB FIFO Message Count
bits : 11 - 14 (4 bit)
access : read-only
Global AFL Ignore Entry Register
address_offset : 0x1324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRN : Ignore Rule Number
bits : 0 - 7 (8 bit)
access : read-write
ICN : Ignore Channel Number
bits : 16 - 17 (2 bit)
access : read-write
Global AFL Ignore Control Register
address_offset : 0x1328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IREN : Ignore Rule Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AFL entry number does not ignore
#1 : 1
AFL entry number ignores
End of enumeration elements list.
KEY : Key code
bits : 8 - 14 (7 bit)
access : write-only
DMA Transfer Control Register
address_offset : 0x1330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFDMAE0 : DMA Transfer Enable for RXFIFO 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled
#1 : 1
DMA Transfer Request enabled
End of enumeration elements list.
RFDMAE1 : DMA Transfer Enable for RXFIFO 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled
#1 : 1
DMA Transfer Request enabled
End of enumeration elements list.
RFDMAE2 : DMA Transfer Enable for RXFIFO 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled
#1 : 1
DMA Transfer Request enabled
End of enumeration elements list.
RFDMAE3 : DMA Transfer Enable for RXFIFO 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled
#1 : 1
DMA Transfer Request enabled
End of enumeration elements list.
RFDMAE4 : DMA Transfer Enable for RXFIFO 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled
#1 : 1
DMA Transfer Request enabled
End of enumeration elements list.
RFDMAE5 : DMA Transfer Enable for RXFIFO 5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled
#1 : 1
DMA Transfer Request enabled
End of enumeration elements list.
RFDMAE6 : DMA Transfer Enable for RXFIFO 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled
#1 : 1
DMA Transfer Request enabled
End of enumeration elements list.
RFDMAE7 : DMA Transfer Enable for RXFIFO 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled
#1 : 1
DMA Transfer Request enabled
End of enumeration elements list.
CFDMAE0 : DMA Transfer Enable for Common FIFO 0 of channel 0
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled for channel n
#1 : 1
DMA Transfer Request enabled for channel n
End of enumeration elements list.
CFDMAE1 : DMA Transfer Enable for Common FIFO 0 of channel 1
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA Transfer Request disabled for channel n
#1 : 1
DMA Transfer Request enabled for channel n
End of enumeration elements list.
DMA Transfer Status Register
address_offset : 0x1334 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFDMASTS0 : DMA Transfer Status for RX FIFO 0
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
RFDMASTS1 : DMA Transfer Status for RX FIFO 1
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
RFDMASTS2 : DMA Transfer Status for RX FIFO 2
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
RFDMASTS3 : DMA Transfer Status for RX FIFO 3
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
RFDMASTS4 : DMA Transfer Status for RX FIFO 4
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
RFDMASTS5 : DMA Transfer Status for RX FIFO 5
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
RFDMASTS6 : DMA Transfer Status for RX FIFO 6
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
RFDMASTS7 : DMA Transfer Status for RX FIFO 7
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
CFDMASTS0 : DMA Transfer Status only for Common FIFO 0 of channel 0
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
CFDMASTS1 : DMA Transfer Status only for Common FIFO 0 of channel 1
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer ongoing
End of enumeration elements list.
Common FIFO Configuration / Control Registers %s
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFE : Common FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
CFRXIE : Common FIFO RX Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame RX
#1 : 1
FIFO Interrupt generation enabled for Frame RX
End of enumeration elements list.
CFTXIE : Common FIFO TX Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled for Frame TX
#1 : 1
FIFO Interrupt generation enabled for Frame TX
End of enumeration elements list.
CFPLS : Common FIFO Payload Data size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bytes
#001 : 001
12 bytes
#010 : 010
16 bytes
#011 : 011
20 bytes
#100 : 100
24 bytes
#101 : 101
32 bytes
#110 : 110
48 bytes
#111 : 111
64 bytes
End of enumeration elements list.
CFM : Common FIFO Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
RX FIFO Mode
#01 : 01
TX FIFO Mode
#10 : 10
CAN – CAN GW FIFO Mode
#11 : 11
Reserved
End of enumeration elements list.
CFITSS : Common FIFO Interval Timer Source Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock (×1 / ×10 period)
#1 : 1
Bit Time Clock of related channel (FIFO is linked to fixed channel)
End of enumeration elements list.
CFITR : Common FIFO Interval Timer Resolution
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reference Clock Period ×1
#1 : 1
Reference Clock Period ×10
End of enumeration elements list.
CFIM : Common FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO Mode: RX Interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO Mode: TX Interrupt generated when Common FIFO transmits the last message successfully GW FIFO Mode: For RX interrupt flag: Interrupt generated when FIFO counter increments and reaches the value configured in CFIGCV For TX interrupt flag: Interrupt generated when FIFO transmits the last message successfully
#1 : 1
RX FIFO Mode: RX Interrupt generated at the end of every received message storage TX FIFO Mode: Interrupt generated for every successfully transmitted message GW FIFO Mode: For RX interrupt flag: Interrupt generated when a message is stored in the FIFO For TX interrupt flag: Interrupt generated when a message is successfully transmitted from the FIFO
End of enumeration elements list.
CFIGCV : Common FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
CFTML : Common FIFO TX Message Buffer Link
bits : 16 - 19 (4 bit)
access : read-write
CFDC : Common FIFO Depth Configuration
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
CFITT : Common FIFO Interval Transmission Time
bits : 24 - 30 (7 bit)
access : read-write
DMA TX Transfer Control Register
address_offset : 0x1340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TQ0DMAE0 : DMA TX Transfer Enable for TXQ 0 of channel 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA TX Transfer Request disabled
#1 : 1
DMA TX Transfer Request enabled
End of enumeration elements list.
TQ0DMAE1 : DMA TX Transfer Enable for TXQ 0 of channel 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA TX Transfer Request disabled
#1 : 1
DMA TX Transfer Request enabled
End of enumeration elements list.
TQ3DMAE0 : DMA TX Transfer Enable for TXQ 3 of channel 0
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA TX Transfer Request disabled
#1 : 1
DMA TX Transfer Request enabled
End of enumeration elements list.
TQ3DMAE1 : DMA TX Transfer Enable for TXQ 3 of channel 1
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA TX Transfer Request disabled
#1 : 1
DMA TX Transfer Request enabled
End of enumeration elements list.
CFDMAE0 : DMA TX Transfer Enable for Common FIFO 2 of channel 0
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA TX Transfer Request disabled for channel n
#1 : 1
DMA TX Transfer Request enabled for channel n
End of enumeration elements list.
CFDMAE1 : DMA TX Transfer Enable for Common FIFO 2 of channel 1
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA TX Transfer Request disabled for channel n
#1 : 1
DMA TX Transfer Request enabled for channel n
End of enumeration elements list.
DMA TX Transfer Status Register
address_offset : 0x1344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TQ0DMASTS0 : DMA TX Transfer Status for TXQ0 of channel 0
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer enable
End of enumeration elements list.
TQ0DMASTS1 : DMA TX Transfer Status for TXQ0 of channel 1
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer enable
End of enumeration elements list.
TQ3DMASTS0 : DMA TX Transfer Status for TXQ3 of channel 0
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer enable
End of enumeration elements list.
TQ3DMASTS1 : DMA TX Transfer Status for TXQ3 of channel 1
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer enable
End of enumeration elements list.
CFDMASTS0 : DMA TX Transfer Status only for Common FIFO 2 of channel 0
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer enable
End of enumeration elements list.
CFDMASTS1 : DMA TX Transfer Status only for Common FIFO 2 of channel 1
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMA transfer stopped
#1 : 1
DMA transfer enable
End of enumeration elements list.
Global RX Interrupt Status Register %s
address_offset : 0x1350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QFIF : TXQ Full Interrupt Flag Channel n
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding TXQ Full interrupt flag is not set
#1 : 1
Corresponding TXQ Full interrupt flag is set
End of enumeration elements list.
QOFRIF : TXQ One Frame RX Interrupt Flag Channel n
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding TXQ One Frame RX interrupt flag is not set
#1 : 1
Corresponding TXQ One Frame RX interrupt flag is set
End of enumeration elements list.
CFRIF : Common FIFO RX Interrupt Flag Channel n
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO RX interrupt flag is not set
#1 : 1
Corresponding Common FIFO RX interrupt flag is set
End of enumeration elements list.
CFRFIF : Common FIFO FDC level Full Interrupt Flag Channel n
bits : 24 - 25 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO Full interrupt flag is not set
#1 : 1
Corresponding Common FIFO Full interrupt flag is set
End of enumeration elements list.
CFOFRIF : Common FIFO One Frame RX Interrupt Flag Channel n
bits : 28 - 29 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO One Frame RX interrupt flag is not set
#1 : 1
Corresponding Common FIFO One Frame RX interrupt flag is set
End of enumeration elements list.
Global RX Interrupt Status Register %s
address_offset : 0x1354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QFIF : TXQ Full Interrupt Flag Channel n
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding TXQ Full interrupt flag is not set
#1 : 1
Corresponding TXQ Full interrupt flag is set
End of enumeration elements list.
QOFRIF : TXQ One Frame RX Interrupt Flag Channel n
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding TXQ One Frame RX interrupt flag is not set
#1 : 1
Corresponding TXQ One Frame RX interrupt flag is set
End of enumeration elements list.
CFRIF : Common FIFO RX Interrupt Flag Channel n
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO RX interrupt flag is not set
#1 : 1
Corresponding Common FIFO RX interrupt flag is set
End of enumeration elements list.
CFRFIF : Common FIFO FDC level Full Interrupt Flag Channel n
bits : 24 - 25 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO Full interrupt flag is not set
#1 : 1
Corresponding Common FIFO Full interrupt flag is set
End of enumeration elements list.
CFOFRIF : Common FIFO One Frame RX Interrupt Flag Channel n
bits : 28 - 29 (2 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO One Frame RX interrupt flag is not set
#1 : 1
Corresponding Common FIFO One Frame RX interrupt flag is set
End of enumeration elements list.
Global SW reset Register
address_offset : 0x1380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRST : SW reset
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
normal state
#1 : 1
SW reset state
End of enumeration elements list.
KEY : Key code
bits : 8 - 14 (7 bit)
access : write-only
Channel %s Control Registers
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHMDC : Channel Mode Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Channel Operation Mode request
#01 : 01
Channel Reset request
#10 : 10
Channel Halt request
#11 : 11
Keep current value
End of enumeration elements list.
CSLPR : Channel Sleep Request
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Sleep Request disabled
#1 : 1
Channel Sleep Request enabled
End of enumeration elements list.
RTBO : Return from Bus-Off
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel is not forced to return from Bus-Off
#1 : 1
Channel is forced to return from Bus-Off
End of enumeration elements list.
BEIE : Bus Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus Error Interrupt disabled
#1 : 1
Bus Error Interrupt enabled
End of enumeration elements list.
EWIE : Error Warning Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error Warning Interrupt disabled
#1 : 1
Error Warning Interrupt enabled
End of enumeration elements list.
EPIE : Error Passive Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error Passive Interrupt disabled
#1 : 1
Error Passive Interrupt enabled
End of enumeration elements list.
BOEIE : Bus-Off Entry Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus-Off Entry Interrupt disabled
#1 : 1
Bus-Off Entry Interrupt enabled
End of enumeration elements list.
BORIE : Bus-Off Recovery Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus-Off Recovery Interrupt disabled
#1 : 1
Bus-Off Recovery Interrupt enabled
End of enumeration elements list.
OLIE : Overload Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Overload Interrupt disabled
#1 : 1
Overload Interrupt enabled
End of enumeration elements list.
BLIE : Bus Lock Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus Lock Interrupt disabled
#1 : 1
Bus Lock Interrupt enabled
End of enumeration elements list.
ALIE : Arbitration Lost Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Arbitration Lost Interrupt disabled
#1 : 1
Arbitration Lost Interrupt enabled
End of enumeration elements list.
TAIE : Transmission abort Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX abort Interrupt disabled
#1 : 1
TX abort Interrupt enabled
End of enumeration elements list.
EOCOIE : Error occurrence counter overflow Interrupt enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error occurrence counter overflow Interrupt disabled
#1 : 1
Error occurrence counter overflow Interrupt enabled
End of enumeration elements list.
SOCOIE : Successful Occurrence Counter Overflow Interrupt enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Successful occurrence counter overflow interrupt disabled
#1 : 1
Successful occurrence counter overflow interrupt enabled
End of enumeration elements list.
TDCVFIE : Transceiver Delay Compensation Violation Interrupt enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transceiver Delay Compensation Violation Interrupt disabled
#1 : 1
Transceiver Delay Compensation Violation Interrupt enabled
End of enumeration elements list.
BOM : Channel Bus-Off Mode
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#00 : 00
Normal mode (comply with ISO 11898-1)
#01 : 01
Entry to Halt Mode automatically at Bus-Off start
#10 : 10
Entry to Halt Mode automatically at Bus-Off end
#11 : 11
Entry to Halt Mode (during Bus-Off Recovery Period) by S/W
End of enumeration elements list.
ERRD : Channel Error Display
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Only the 1st set of error codes displayed
#1 : 1
Accumulated error codes displayed
End of enumeration elements list.
CTME : Channel Test Mode Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Test Mode disabled
#1 : 1
Channel Test Mode enabled
End of enumeration elements list.
CTMS : Channel Test Mode Select
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#00 : 00
Basic test mode
#01 : 01
Listen-Only mode
#10 : 10
Self test mode 0 (External Loop back mode)
#11 : 11
Self test mode 1 (Internal Loop back mode)
End of enumeration elements list.
TRWE : TEC/REC Write Enable
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error Counter write disabled
#1 : 1
Error Counter write enabled
End of enumeration elements list.
TRH : TEC/REC Hold
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error counter normal operation
#1 : 1
Error counter frozen
End of enumeration elements list.
TRR : TEC/REC Reset
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error counter normal operation
#1 : 1
Error counter reset
End of enumeration elements list.
CRCT : CRC Error Test
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
First data bit of reception stream not inverted
#1 : 1
First data bit of reception stream inverted
End of enumeration elements list.
ROM : Restricted Operation Mode
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Restricted Operation Mode disabled
#1 : 1
Restricted Operation Mode enabled
End of enumeration elements list.
Channel %s Data Bitrate Configuration Register
address_offset : 0x1400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBRP : Channel Data Baud Rate Prescaler
bits : 0 - 6 (7 bit)
access : read-write
DTSEG1 : Timing Segment 1
bits : 8 - 11 (4 bit)
access : read-write
DTSEG2 : Timing Segment 2
bits : 16 - 18 (3 bit)
access : read-write
DSJW : Resynchronization Jump Width
bits : 24 - 26 (3 bit)
access : read-write
Channel %s CAN-FD Configuration Register
address_offset : 0x1404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCCFG : Error Occurrence Counter Configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
All Transmitter or Receiver CAN Frames
#001 : 001
All Transmitter CAN Frames
#010 : 010
All Receiver CAN Frames
#011 : 011
Reserved
#100 : 100
Only Transmitter or Receiver CAN-FD Data-Phase (fast bits)
#101 : 101
Only Transmitter CAN-FD Data-Phase (fast bits)
#110 : 110
Only Receiver CAN-FD Data-Phase (fast bits)
#111 : 111
Reserved
End of enumeration elements list.
TDCOC : Transceiver Delay Compensation Offset Configuration
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Measured + offset
#1 : 1
offset only
End of enumeration elements list.
TDCE : Transceiver Delay Compensation Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transceiver Delay Compensation disabled
#1 : 1
Transceiver Delay Compensation enabled
End of enumeration elements list.
ESIC : Error State Indication Configuration
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
The ESI bit in the frame will be representing the Error state of the node itself.
#1 : 1
The ESI bit in the frame will be representing the Error state of message buffer if the node itself is not in error passive. If the node is in Error Passive then the ESI bit will be driven by the node itself.
End of enumeration elements list.
TDCO : Transceiver Delay Compensation Offset
bits : 16 - 22 (7 bit)
access : read-write
GWEN : CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Multi Gateway Disabled
#1 : 1
Multi Gateway Enable
End of enumeration elements list.
GWFDF : Gateway FDF configuration bit
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
GW frame is transmitted as Classical CAN frame.
#1 : 1
GW frame is transmitted as CAN-FD frame .
End of enumeration elements list.
GWBRS : Gateway BRS configuration bit
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
GW frame is transmitted with BRS = 0
#1 : 1
GW frame is transmitted with BRS = 1
End of enumeration elements list.
FDOE : FD only enable
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
FD only mode disabled
#1 : 1
FD only mode enabled
End of enumeration elements list.
REFE : RX edge filter enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX edge filter disabled
#1 : 1
RX edge filter enabled
End of enumeration elements list.
CLOE : Classical CAN only enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Classical only mode disabled
#1 : 1
Classical only mode enabled
End of enumeration elements list.
CFDTE : CAN-FD frame Distinction enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
CAN-FD frame distinction disabled
#1 : 1
CAN-FD frame distinction enabled
End of enumeration elements list.
Channel %s CAN-FD Control Register
address_offset : 0x1408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCCLR : Error Occurrence Counter Clear
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Error Occurrence Counter clear
#1 : 1
Clear Error Occurrence Counter
End of enumeration elements list.
SOCCLR : Successful Occurrence Counter Clear
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Successful Occurrence Counter clear
#1 : 1
Clear Successful Occurrence Counter
End of enumeration elements list.
Channel %s CAN-FD Status Register
address_offset : 0x140C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCR : Transceiver Delay Compensation Result
bits : 0 - 6 (7 bit)
access : read-only
EOCO : Error occurrence counter overflow
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error occurrence counter has not overflowed
#1 : 1
Error occurrence counter has overflowed
End of enumeration elements list.
SOCO : Successful occurrence counter overflow
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Successful occurrence counter has not overflowed
#1 : 1
Successful occurrence counter has overflowed
End of enumeration elements list.
TDCVF : Transceiver Delay Compensation Violation Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transceiver Delay Compensation Violation has not occurred
#1 : 1
Transceiver Delay Compensation Violation has occurred
End of enumeration elements list.
EOC : Error occurrence counter register
bits : 16 - 22 (7 bit)
access : read-only
SOC : Successful occurrence counter register
bits : 24 - 30 (7 bit)
access : read-only
Channel %s CAN-FD CRC Register
address_offset : 0x1410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCREG : CRC Register value
bits : 0 - 19 (20 bit)
access : read-only
SCNT : Stuff bit count
bits : 24 - 26 (3 bit)
access : read-only
Channel %s Bus load Control Register
address_offset : 0x1418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLCE : BUS Load counter Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
BUS Load counter disable
#1 : 1
BUS Load counter enable
End of enumeration elements list.
BLCLD : BUS Load counter load
bits : 8 - 7 (0 bit)
access : write-only
Channel %s Bus load Status Register
address_offset : 0x141C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLC : BUS Load counter Status
bits : 3 - 30 (28 bit)
access : read-only
Channel %s Data Bitrate Configuration Register
address_offset : 0x1420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBRP : Channel Data Baud Rate Prescaler
bits : 0 - 6 (7 bit)
access : read-write
DTSEG1 : Timing Segment 1
bits : 8 - 11 (4 bit)
access : read-write
DTSEG2 : Timing Segment 2
bits : 16 - 18 (3 bit)
access : read-write
DSJW : Resynchronization Jump Width
bits : 24 - 26 (3 bit)
access : read-write
Channel %s CAN-FD Configuration Register
address_offset : 0x1424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCCFG : Error Occurrence Counter Configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
All Transmitter or Receiver CAN Frames
#001 : 001
All Transmitter CAN Frames
#010 : 010
All Receiver CAN Frames
#011 : 011
Reserved
#100 : 100
Only Transmitter or Receiver CAN-FD Data-Phase (fast bits)
#101 : 101
Only Transmitter CAN-FD Data-Phase (fast bits)
#110 : 110
Only Receiver CAN-FD Data-Phase (fast bits)
#111 : 111
Reserved
End of enumeration elements list.
TDCOC : Transceiver Delay Compensation Offset Configuration
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Measured + offset
#1 : 1
offset only
End of enumeration elements list.
TDCE : Transceiver Delay Compensation Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transceiver Delay Compensation disabled
#1 : 1
Transceiver Delay Compensation enabled
End of enumeration elements list.
ESIC : Error State Indication Configuration
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
The ESI bit in the frame will be representing the Error state of the node itself.
#1 : 1
The ESI bit in the frame will be representing the Error state of message buffer if the node itself is not in error passive. If the node is in Error Passive then the ESI bit will be driven by the node itself.
End of enumeration elements list.
TDCO : Transceiver Delay Compensation Offset
bits : 16 - 22 (7 bit)
access : read-write
GWEN : CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Multi Gateway Disabled
#1 : 1
Multi Gateway Enable
End of enumeration elements list.
GWFDF : Gateway FDF configuration bit
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
GW frame is transmitted as Classical CAN frame.
#1 : 1
GW frame is transmitted as CAN-FD frame .
End of enumeration elements list.
GWBRS : Gateway BRS configuration bit
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
GW frame is transmitted with BRS = 0
#1 : 1
GW frame is transmitted with BRS = 1
End of enumeration elements list.
FDOE : FD only enable
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
FD only mode disabled
#1 : 1
FD only mode enabled
End of enumeration elements list.
REFE : RX edge filter enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX edge filter disabled
#1 : 1
RX edge filter enabled
End of enumeration elements list.
CLOE : Classical CAN only enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Classical only mode disabled
#1 : 1
Classical only mode enabled
End of enumeration elements list.
CFDTE : CAN-FD frame Distinction enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
CAN-FD frame distinction disabled
#1 : 1
CAN-FD frame distinction enabled
End of enumeration elements list.
Channel %s CAN-FD Control Register
address_offset : 0x1428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCCLR : Error Occurrence Counter Clear
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Error Occurrence Counter clear
#1 : 1
Clear Error Occurrence Counter
End of enumeration elements list.
SOCCLR : Successful Occurrence Counter Clear
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Successful Occurrence Counter clear
#1 : 1
Clear Successful Occurrence Counter
End of enumeration elements list.
Channel %s CAN-FD Status Register
address_offset : 0x142C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCR : Transceiver Delay Compensation Result
bits : 0 - 6 (7 bit)
access : read-only
EOCO : Error occurrence counter overflow
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error occurrence counter has not overflowed
#1 : 1
Error occurrence counter has overflowed
End of enumeration elements list.
SOCO : Successful occurrence counter overflow
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Successful occurrence counter has not overflowed
#1 : 1
Successful occurrence counter has overflowed
End of enumeration elements list.
TDCVF : Transceiver Delay Compensation Violation Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transceiver Delay Compensation Violation has not occurred
#1 : 1
Transceiver Delay Compensation Violation has occurred
End of enumeration elements list.
EOC : Error occurrence counter register
bits : 16 - 22 (7 bit)
access : read-only
SOC : Successful occurrence counter register
bits : 24 - 30 (7 bit)
access : read-only
Channel %s CAN-FD CRC Register
address_offset : 0x1430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCREG : CRC Register value
bits : 0 - 19 (20 bit)
access : read-only
SCNT : Stuff bit count
bits : 24 - 26 (3 bit)
access : read-only
Channel %s Bus load Control Register
address_offset : 0x1438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLCE : BUS Load counter Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
BUS Load counter disable
#1 : 1
BUS Load counter enable
End of enumeration elements list.
BLCLD : BUS Load counter load
bits : 8 - 7 (0 bit)
access : write-only
Channel %s Bus load Status Register
address_offset : 0x143C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLC : BUS Load counter Status
bits : 3 - 30 (28 bit)
access : read-only
Channel %s Status Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRSTSTS : Channel RESET Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Reset Mode
#1 : 1
Channel in Reset Mode
End of enumeration elements list.
CHLTSTS : Channel HALT Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Halt Mode
#1 : 1
Channel in Halt Mode
End of enumeration elements list.
CSLPSTS : Channel SLEEP Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Sleep Mode
#1 : 1
Channel in Sleep Mode
End of enumeration elements list.
EPSTS : Channel Error Passive Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Error Passive state
#1 : 1
Channel in Error Passive state
End of enumeration elements list.
BOSTS : Channel Bus-Off Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Bus-Off state
#1 : 1
Channel in Bus-Off state
End of enumeration elements list.
TRMSTS : Channel Transmit Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel is not transmitting
#1 : 1
Channel is transmitting
End of enumeration elements list.
RECSTS : Channel Receive Status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel is not receiving
#1 : 1
Channel is receiving
End of enumeration elements list.
COMSTS : Channel Communication Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel is not ready for communication
#1 : 1
Channel is ready for communication
End of enumeration elements list.
ESIF : Error State Indication Flag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
No CAN-FD message has been received with the ESI flag was set
#1 : 1
At least 1 CAN-FD message was received where the ESI flag was set
End of enumeration elements list.
REC : Reception Error Count
bits : 16 - 22 (7 bit)
access : read-only
TEC : Transmission Error Count
bits : 24 - 30 (7 bit)
access : read-write
Common FIFO Configuration / Control Enhancement Registers %s
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFFIE : Common FIFO Full interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
CFOFRXIE : Common FIFO One Frame Reception Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
CFOFTXIE : Common FIFO One Frame Transmission Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
CFMOWM : Common FIFO message overwrite mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Message discarded mode
#1 : 1
Message overwrite mode
End of enumeration elements list.
CFBME : Common FIFO Buffering Mode Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmission from Common FIFO
#1 : 1
Transmission halt from Common FIFO
End of enumeration elements list.
Global Acceptance Filter List ID Registers
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x180C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x1810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x181C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x1820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x182C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x1830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x183C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Common FIFO Configuration / Control Enhancement Registers %s
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFFIE : Common FIFO Full interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
CFOFRXIE : Common FIFO One Frame Reception Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
CFOFTXIE : Common FIFO One Frame Transmission Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
CFMOWM : Common FIFO message overwrite mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Message discarded mode
#1 : 1
Message overwrite mode
End of enumeration elements list.
CFBME : Common FIFO Buffering Mode Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmission from Common FIFO
#1 : 1
Transmission halt from Common FIFO
End of enumeration elements list.
Global Acceptance Filter List ID Registers
address_offset : 0x1840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x184C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x1850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x185C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x1860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x186C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x1870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x187C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Common FIFO Configuration / Control Enhancement Registers %s
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFFIE : Common FIFO Full interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
CFOFRXIE : Common FIFO One Frame Reception Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
CFOFTXIE : Common FIFO One Frame Transmission Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
CFMOWM : Common FIFO message overwrite mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Message discarded mode
#1 : 1
Message overwrite mode
End of enumeration elements list.
CFBME : Common FIFO Buffering Mode Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmission from Common FIFO
#1 : 1
Transmission halt from Common FIFO
End of enumeration elements list.
Global Acceptance Filter List ID Registers
address_offset : 0x1880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x188C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x1890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x1894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x1898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x189C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x18A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x18A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x18A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x18AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x18B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x18B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x18B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x18BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Common FIFO Configuration / Control Enhancement Registers %s
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFFIE : Common FIFO Full interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
CFOFRXIE : Common FIFO One Frame Reception Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
CFOFTXIE : Common FIFO One Frame Transmission Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
CFMOWM : Common FIFO message overwrite mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Message discarded mode
#1 : 1
Message overwrite mode
End of enumeration elements list.
CFBME : Common FIFO Buffering Mode Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmission from Common FIFO
#1 : 1
Transmission halt from Common FIFO
End of enumeration elements list.
Global Acceptance Filter List ID Registers
address_offset : 0x18C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x18C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x18C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x18CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x18D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x18D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x18D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x18E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x18E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x18E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x18EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Global Acceptance Filter List ID Registers
address_offset : 0x18F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLID : Global Acceptance Filter List Entry ID Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLLB : Global Acceptance Filter List Entry Loopback Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘RX’
#1 : 1
Global Acceptance Filter List entry ID for acceptance filtering has attribute ‘TX’
End of enumeration elements list.
GAFLRTR : Global Acceptance Filter List Entry RTR Field
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data Frame
#1 : 1
Remote Frame
End of enumeration elements list.
GAFLIDE : Global Acceptance Filter List Entry IDE Field
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard Identifier of Rule entry ID is valid for acceptance filtering
#1 : 1
Extended Identifier of Rule entry ID is valid for acceptance filtering
End of enumeration elements list.
Global Acceptance Filter List Mask Registers
address_offset : 0x18F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLIDM : Global Acceptance Filter List ID Mask Field
bits : 0 - 27 (28 bit)
access : read-write
GAFLIFL1 : Global Acceptance Filter List Information Label 1
bits : 29 - 28 (0 bit)
access : read-write
GAFLRTRM : Global Acceptance Filter List Entry RTR Mask
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTR bit is not considered for ID matching
#1 : 1
RTR bit is considered for ID matching
End of enumeration elements list.
GAFLIDEM : Global Acceptance Filter List IDE Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
IDE bit is not considered for ID matching
#1 : 1
IDE bit is considered for ID matching
End of enumeration elements list.
Global Acceptance Filter List Pointer 0 Registers
address_offset : 0x18F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLDLC : Global Acceptance Filter List DLC Field
bits : 0 - 2 (3 bit)
access : read-write
GAFLSRD0 : Global Acceptance Filter List Select Routing destination 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO0
#1 : 1
Routing target is TX Queue 0 instead of CFIFO0
End of enumeration elements list.
GAFLSRD1 : Global Acceptance Filter List Select Routing destination 1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO1
#1 : 1
Routing target is TX Queue 1 instead of CFIFO1
End of enumeration elements list.
GAFLSRD2 : Global Acceptance Filter List Select Routing destination 2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Routing target is CFIFO2
#1 : 1
Routing target is TX Queue 2 instead of CFIFO2
End of enumeration elements list.
GAFLIFL0 : Global Acceptance Filter List Information Label 0
bits : 7 - 6 (0 bit)
access : read-write
GAFLRMDP : Global Acceptance Filter List RX Message Buffer Direction Pointer
bits : 8 - 11 (4 bit)
access : read-write
GAFLRMV : Global Acceptance Filter List RX Message Buffer Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Acceptance Filter List Single Message Buffer Direction Pointer is invalid
#1 : 1
Global Acceptance Filter List Single Message Buffer Direction Pointer is valid
End of enumeration elements list.
GAFLPTR : Global Acceptance Filter List Pointer Field
bits : 16 - 30 (15 bit)
access : read-write
Global Acceptance Filter List Pointer 1 Registers
address_offset : 0x18FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAFLFDP : Global Acceptance Filter List FIFO Direction Pointer
bits : 0 - 12 (13 bit)
access : read-write
Common FIFO Configuration / Control Enhancement Registers %s
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFFIE : Common FIFO Full interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
CFOFRXIE : Common FIFO One Frame Reception Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
CFOFTXIE : Common FIFO One Frame Transmission Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
CFMOWM : Common FIFO message overwrite mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Message discarded mode
#1 : 1
Message overwrite mode
End of enumeration elements list.
CFBME : Common FIFO Buffering Mode Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmission from Common FIFO
#1 : 1
Transmission halt from Common FIFO
End of enumeration elements list.
Common FIFO Configuration / Control Enhancement Registers %s
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFFIE : Common FIFO Full interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
CFOFRXIE : Common FIFO One Frame Reception Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame RX Interrupt generation disabled
#1 : 1
One Frame RX Interrupt generation enabled
End of enumeration elements list.
CFOFTXIE : Common FIFO One Frame Transmission Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
One Frame TX Interrupt generation disabled
#1 : 1
One Frame TX Interrupt generation enabled
End of enumeration elements list.
CFMOWM : Common FIFO message overwrite mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Message discarded mode
#1 : 1
Message overwrite mode
End of enumeration elements list.
CFBME : Common FIFO Buffering Mode Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmission from Common FIFO
#1 : 1
Transmission halt from Common FIFO
End of enumeration elements list.
Channel %s Error Flag Registers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BEF : Bus Error Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bus Error not detected
#1 : 1
Channel Bus Error detected
End of enumeration elements list.
EWF : Error Warning Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Error Warning not detected
#1 : 1
Channel Error Warning detected
End of enumeration elements list.
EPF : Error Passive Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Error Passive not detected
#1 : 1
Channel Error Passive detected
End of enumeration elements list.
BOEF : Bus-Off Entry Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bus-Off Entry not detected
#1 : 1
Channel Bus-Off Entry detected
End of enumeration elements list.
BORF : Bus-Off Recovery Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bus-Off Recovery not detected
#1 : 1
Channel Bus-Off Recovery detected
End of enumeration elements list.
OVLF : Overload Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Overload not detected
#1 : 1
Channel Overload detected
End of enumeration elements list.
BLF : Bus Lock Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bus Lock not detected
#1 : 1
Channel Bus Lock detected
End of enumeration elements list.
ALF : Arbitration Lost Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Arbitration Lost not detected
#1 : 1
Channel Arbitration Lost detected
End of enumeration elements list.
SERR : Stuff Error
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel stuff Error not detected
#1 : 1
Channel stuff Error detected
End of enumeration elements list.
FERR : Form Error
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Form Error not detected
#1 : 1
Channel Form Error detected
End of enumeration elements list.
AERR : Acknowledge Error
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Ack Error not detected
#1 : 1
Channel Ack Error detected
End of enumeration elements list.
CERR : CRC Error
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel CRC Error not detected
#1 : 1
Channel CRC Error detected
End of enumeration elements list.
B1ERR : Bit 1 Error
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bit 1 Error not detected
#1 : 1
Channel Bit 1 Error detected
End of enumeration elements list.
B0ERR : Bit 0 Error
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bit 0 Error not detected
#1 : 1
Channel Bit 0 Error detected
End of enumeration elements list.
ADERR : Acknowledge Delimiter Error
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Ack Del Error not detected
#1 : 1
Channel Ack Del Error detected
End of enumeration elements list.
CRCREG : CRC Register value
bits : 16 - 29 (14 bit)
access : read-only
Common FIFO Status Registers %s
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFEMP : Common FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
CFFLL : Common FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
CFMLT : Common FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
CFRXIF : Common RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Reception
#1 : 1
FIFO Interrupt condition satisfied after Frame Reception
End of enumeration elements list.
CFTXIF : Common TX FIFO Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Transmission
#1 : 1
FIFO Interrupt condition satisfied after Frame Transmission
End of enumeration elements list.
CFMC : Common FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
CFFIF : Common FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt condition not satisfied for FIFO Full interrupt
#1 : 1
Interrupt condition satisfied for FIFO Full interrupt
End of enumeration elements list.
CFOFRXIF : Common FIFO One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
CFOFTXIF : Common FIFO One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
CFMOW : Common FIFO message overwrite
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message overwrite occurred in FIFO
#1 : 1
Message overwrite occurred in FIFO
End of enumeration elements list.
Common FIFO Status Registers %s
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFEMP : Common FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
CFFLL : Common FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
CFMLT : Common FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
CFRXIF : Common RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Reception
#1 : 1
FIFO Interrupt condition satisfied after Frame Reception
End of enumeration elements list.
CFTXIF : Common TX FIFO Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Transmission
#1 : 1
FIFO Interrupt condition satisfied after Frame Transmission
End of enumeration elements list.
CFMC : Common FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
CFFIF : Common FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt condition not satisfied for FIFO Full interrupt
#1 : 1
Interrupt condition satisfied for FIFO Full interrupt
End of enumeration elements list.
CFOFRXIF : Common FIFO One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
CFOFTXIF : Common FIFO One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
CFMOW : Common FIFO message overwrite
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message overwrite occurred in FIFO
#1 : 1
Message overwrite occurred in FIFO
End of enumeration elements list.
Common FIFO Status Registers %s
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFEMP : Common FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
CFFLL : Common FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
CFMLT : Common FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
CFRXIF : Common RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Reception
#1 : 1
FIFO Interrupt condition satisfied after Frame Reception
End of enumeration elements list.
CFTXIF : Common TX FIFO Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Transmission
#1 : 1
FIFO Interrupt condition satisfied after Frame Transmission
End of enumeration elements list.
CFMC : Common FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
CFFIF : Common FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt condition not satisfied for FIFO Full interrupt
#1 : 1
Interrupt condition satisfied for FIFO Full interrupt
End of enumeration elements list.
CFOFRXIF : Common FIFO One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
CFOFTXIF : Common FIFO One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
CFMOW : Common FIFO message overwrite
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message overwrite occurred in FIFO
#1 : 1
Message overwrite occurred in FIFO
End of enumeration elements list.
Common FIFO Status Registers %s
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFEMP : Common FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
CFFLL : Common FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
CFMLT : Common FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
CFRXIF : Common RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Reception
#1 : 1
FIFO Interrupt condition satisfied after Frame Reception
End of enumeration elements list.
CFTXIF : Common TX FIFO Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Transmission
#1 : 1
FIFO Interrupt condition satisfied after Frame Transmission
End of enumeration elements list.
CFMC : Common FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
CFFIF : Common FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt condition not satisfied for FIFO Full interrupt
#1 : 1
Interrupt condition satisfied for FIFO Full interrupt
End of enumeration elements list.
CFOFRXIF : Common FIFO One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
CFOFTXIF : Common FIFO One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
CFMOW : Common FIFO message overwrite
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message overwrite occurred in FIFO
#1 : 1
Message overwrite occurred in FIFO
End of enumeration elements list.
Common FIFO Status Registers %s
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFEMP : Common FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
CFFLL : Common FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
CFMLT : Common FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
CFRXIF : Common RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Reception
#1 : 1
FIFO Interrupt condition satisfied after Frame Reception
End of enumeration elements list.
CFTXIF : Common TX FIFO Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Transmission
#1 : 1
FIFO Interrupt condition satisfied after Frame Transmission
End of enumeration elements list.
CFMC : Common FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
CFFIF : Common FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt condition not satisfied for FIFO Full interrupt
#1 : 1
Interrupt condition satisfied for FIFO Full interrupt
End of enumeration elements list.
CFOFRXIF : Common FIFO One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
CFOFTXIF : Common FIFO One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
CFMOW : Common FIFO message overwrite
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message overwrite occurred in FIFO
#1 : 1
Message overwrite occurred in FIFO
End of enumeration elements list.
Common FIFO Status Registers %s
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFEMP : Common FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
CFFLL : Common FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
CFMLT : Common FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
CFRXIF : Common RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Reception
#1 : 1
FIFO Interrupt condition satisfied after Frame Reception
End of enumeration elements list.
CFTXIF : Common TX FIFO Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied after Frame Transmission
#1 : 1
FIFO Interrupt condition satisfied after Frame Transmission
End of enumeration elements list.
CFMC : Common FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
CFFIF : Common FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt condition not satisfied for FIFO Full interrupt
#1 : 1
Interrupt condition satisfied for FIFO Full interrupt
End of enumeration elements list.
CFOFRXIF : Common FIFO One Frame Reception Interrupt Flag
bits : 17 - 16 (0 bit)
access : read-write
CFOFTXIF : Common FIFO One Frame Transmission Interrupt Flag
bits : 18 - 17 (0 bit)
access : read-write
CFMOW : Common FIFO message overwrite
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message overwrite occurred in FIFO
#1 : 1
Message overwrite occurred in FIFO
End of enumeration elements list.
Common FIFO Pointer Control Registers %s
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFPC : Common FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
Common FIFO Pointer Control Registers %s
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFPC : Common FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
Common FIFO Pointer Control Registers %s
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFPC : Common FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
Common FIFO Pointer Control Registers %s
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFPC : Common FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
Common FIFO Pointer Control Registers %s
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFPC : Common FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
Common FIFO Pointer Control Registers %s
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFPC : Common FIFO Pointer Control
bits : 0 - 6 (7 bit)
access : write-only
FIFO Empty Status Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFXEMP : RX FIF0 Empty Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO not Empty
#1 : 1
Corresponding FIFO Empty
End of enumeration elements list.
CFXEMP : Common FIF0 Empty Status
bits : 8 - 12 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO not Empty
#1 : 1
Corresponding FIFO Empty
End of enumeration elements list.
FIFO Full Status Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFXFLL : RX FIF0 Full Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO not Full
#1 : 1
Corresponding FIFO Full
End of enumeration elements list.
CFXFLL : Common FIF0 Full Status
bits : 8 - 12 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO not Full
#1 : 1
Corresponding FIFO Full
End of enumeration elements list.
FIFO Message Lost Status Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFXMLT : RX FIFO Msg Lost Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO Msg Lost flag not set
#1 : 1
Corresponding FIFO Msg Lost flag set
End of enumeration elements list.
CFXMLT : Common FIFO Msg Lost Status
bits : 8 - 12 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO Msg Lost flag not set
#1 : 1
Corresponding FIFO Msg Lost flag set
End of enumeration elements list.
RX FIFO Interrupt Flag Status Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFXIF : RX FIFO[x] Interrupt Flag Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding RX FIFO interrupt flag not set
#1 : 1
Corresponding RX FIFO interrupt flag set
End of enumeration elements list.
RFXFFLL : RX FIFO[x] Interrupt Full Flag Status
bits : 16 - 22 (7 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding RX FIFO interrupt Full flag not set
#1 : 1
Corresponding RX FIFO interrupt Full flag set
End of enumeration elements list.
Common FIFO RX Interrupt Flag Status Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFXRXIF : Common FIFO [x] RX Interrupt Flag Status
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO RX interrupt flag is not set
#1 : 1
Corresponding Common FIFO RX interrupt flag is set
End of enumeration elements list.
Common FIFO TX Interrupt Flag Status Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFXTXIF : Common FIFO [x] TX Interrupt Flag Status
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO TX interrupt flag is not set
#1 : 1
Corresponding Common FIFO TX interrupt flag is set
End of enumeration elements list.
Common FIFO One Frame RX Interrupt Flag Status Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFXOFRXIF : Common FIFO [x] One Frame RX Interrupt Flag Status
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO One Frame RX interrupt flag is not set
#1 : 1
Corresponding Common FIFO One Frame RX interrupt flag is set
End of enumeration elements list.
Common FIFO One Frame TX Interrupt Flag Status Register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFXOFTXIF : Common FIFO [x] One Frame TX Interrupt Flag Status
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding Common FIFO One Frame TX interrupt flag is not set
#1 : 1
Corresponding Common FIFO One Frame TX interrupt flag is set
End of enumeration elements list.
Common FIFO Message Over Write Status Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFXMOW : Common FIFO [x] Massage overwrite status
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO overwrite flag is not set
#1 : 1
Corresponding FIFO overwrite flag is set
End of enumeration elements list.
FIFO FDC Full Status Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFXFFLL : RX FIFO FDC level full Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO Full interrupt not set
#1 : 1
Corresponding FIFO Full interrupt is set
End of enumeration elements list.
CFXFFLL : COMMON FIFO FDC level full Status
bits : 8 - 12 (5 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding FIFO Full interrupt not set
#1 : 1
Corresponding FIFO Full interrupt is set
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
TX Message Buffer Control Registers %s
address_offset : 0x2D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTR : TX Message Buffer Transmission Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTAR : TX Message Buffer Transmission abort Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TMOM : TX Message Buffer One-shot Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer not configured in one-shot mode
#1 : 1
TX Message Buffer configured in one-shot mode
End of enumeration elements list.
Channel %s Control Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHMDC : Channel Mode Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Channel Operation Mode request
#01 : 01
Channel Reset request
#10 : 10
Channel Halt request
#11 : 11
Keep current value
End of enumeration elements list.
CSLPR : Channel Sleep Request
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Sleep Request disabled
#1 : 1
Channel Sleep Request enabled
End of enumeration elements list.
RTBO : Return from Bus-Off
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel is not forced to return from Bus-Off
#1 : 1
Channel is forced to return from Bus-Off
End of enumeration elements list.
BEIE : Bus Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus Error Interrupt disabled
#1 : 1
Bus Error Interrupt enabled
End of enumeration elements list.
EWIE : Error Warning Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error Warning Interrupt disabled
#1 : 1
Error Warning Interrupt enabled
End of enumeration elements list.
EPIE : Error Passive Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error Passive Interrupt disabled
#1 : 1
Error Passive Interrupt enabled
End of enumeration elements list.
BOEIE : Bus-Off Entry Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus-Off Entry Interrupt disabled
#1 : 1
Bus-Off Entry Interrupt enabled
End of enumeration elements list.
BORIE : Bus-Off Recovery Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus-Off Recovery Interrupt disabled
#1 : 1
Bus-Off Recovery Interrupt enabled
End of enumeration elements list.
OLIE : Overload Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Overload Interrupt disabled
#1 : 1
Overload Interrupt enabled
End of enumeration elements list.
BLIE : Bus Lock Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus Lock Interrupt disabled
#1 : 1
Bus Lock Interrupt enabled
End of enumeration elements list.
ALIE : Arbitration Lost Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Arbitration Lost Interrupt disabled
#1 : 1
Arbitration Lost Interrupt enabled
End of enumeration elements list.
TAIE : Transmission abort Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX abort Interrupt disabled
#1 : 1
TX abort Interrupt enabled
End of enumeration elements list.
EOCOIE : Error occurrence counter overflow Interrupt enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error occurrence counter overflow Interrupt disabled
#1 : 1
Error occurrence counter overflow Interrupt enabled
End of enumeration elements list.
SOCOIE : Successful Occurrence Counter Overflow Interrupt enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Successful occurrence counter overflow interrupt disabled
#1 : 1
Successful occurrence counter overflow interrupt enabled
End of enumeration elements list.
TDCVFIE : Transceiver Delay Compensation Violation Interrupt enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transceiver Delay Compensation Violation Interrupt disabled
#1 : 1
Transceiver Delay Compensation Violation Interrupt enabled
End of enumeration elements list.
BOM : Channel Bus-Off Mode
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#00 : 00
Normal mode (comply with ISO 11898-1)
#01 : 01
Entry to Halt Mode automatically at Bus-Off start
#10 : 10
Entry to Halt Mode automatically at Bus-Off end
#11 : 11
Entry to Halt Mode (during Bus-Off Recovery Period) by S/W
End of enumeration elements list.
ERRD : Channel Error Display
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Only the 1st set of error codes displayed
#1 : 1
Accumulated error codes displayed
End of enumeration elements list.
CTME : Channel Test Mode Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Test Mode disabled
#1 : 1
Channel Test Mode enabled
End of enumeration elements list.
CTMS : Channel Test Mode Select
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#00 : 00
Basic test mode
#01 : 01
Listen-Only mode
#10 : 10
Self test mode 0 (External Loop back mode)
#11 : 11
Self test mode 1 (Internal Loop back mode)
End of enumeration elements list.
TRWE : TEC/REC Write Enable
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error Counter write disabled
#1 : 1
Error Counter write enabled
End of enumeration elements list.
TRH : TEC/REC Hold
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error counter normal operation
#1 : 1
Error counter frozen
End of enumeration elements list.
TRR : TEC/REC Reset
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error counter normal operation
#1 : 1
Error counter reset
End of enumeration elements list.
CRCT : CRC Error Test
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
First data bit of reception stream not inverted
#1 : 1
First data bit of reception stream inverted
End of enumeration elements list.
ROM : Restricted Operation Mode
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Restricted Operation Mode disabled
#1 : 1
Restricted Operation Mode enabled
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
TX Message Buffer Status Registers %s
address_offset : 0x7D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMTSTS : TX Message Buffer Transmission Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No transmission ongoing
#1 : 1
Transmission ongoing
End of enumeration elements list.
TMTRF : TX Message Buffer Transmission Result Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
No Result
#01 : 01
Transmission aborted from the TX MB
#10 : 10
Transmission successful from the TX MB and Transmission abort was not requested
#11 : 11
Transmission successful from the TX MB and Transmission abort was requested
End of enumeration elements list.
TMTRM : TX Message Buffer Transmission Request Mirrored
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer Transmission not requested
#1 : 1
TX Message Buffer Transmission requested
End of enumeration elements list.
TMTARM : TX Message Buffer Transmission abort Request Mirrored
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX Message Buffer transmission request abort not requested
#1 : 1
TX Message Buffer transmission request abort requested
End of enumeration elements list.
Channel %s Status Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRSTSTS : Channel RESET Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Reset Mode
#1 : 1
Channel in Reset Mode
End of enumeration elements list.
CHLTSTS : Channel HALT Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Halt Mode
#1 : 1
Channel in Halt Mode
End of enumeration elements list.
CSLPSTS : Channel SLEEP Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Sleep Mode
#1 : 1
Channel in Sleep Mode
End of enumeration elements list.
EPSTS : Channel Error Passive Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Error Passive state
#1 : 1
Channel in Error Passive state
End of enumeration elements list.
BOSTS : Channel Bus-Off Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel not in Bus-Off state
#1 : 1
Channel in Bus-Off state
End of enumeration elements list.
TRMSTS : Channel Transmit Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel is not transmitting
#1 : 1
Channel is transmitting
End of enumeration elements list.
RECSTS : Channel Receive Status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel is not receiving
#1 : 1
Channel is receiving
End of enumeration elements list.
COMSTS : Channel Communication Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Channel is not ready for communication
#1 : 1
Channel is ready for communication
End of enumeration elements list.
ESIF : Error State Indication Flag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
No CAN-FD message has been received with the ESI flag was set
#1 : 1
At least 1 CAN-FD message was received where the ESI flag was set
End of enumeration elements list.
REC : Reception Error Count
bits : 16 - 22 (7 bit)
access : read-only
TEC : Transmission Error Count
bits : 24 - 30 (7 bit)
access : read-write
Channel %s TX History List Access Registers 0
address_offset : 0x8000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BT : Buffer Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#001 : 001
Flat TX Message Buffer
#010 : 010
TX FIFO MB No and GW FIFO MB No.
#100 : 100
TX Queue MB No.
End of enumeration elements list.
BN : Buffer No.
bits : 3 - 8 (6 bit)
access : read-only
TGW : Transmit Gateway Buffer indication
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
not transmission from Gateway
#1 : 1
transmission from Gateway
End of enumeration elements list.
TMTS : Transmit Timestamp
bits : 16 - 30 (15 bit)
access : read-only
Channel %s TX History List Access Registers 1
address_offset : 0x8004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Transmit ID
bits : 0 - 14 (15 bit)
access : read-only
TIFL : Transmit Information Label
bits : 16 - 16 (1 bit)
access : read-only
Channel %s TX History List Access Registers 0
address_offset : 0x8008 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BT : Buffer Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#001 : 001
Flat TX Message Buffer
#010 : 010
TX FIFO MB No and GW FIFO MB No.
#100 : 100
TX Queue MB No.
End of enumeration elements list.
BN : Buffer No.
bits : 3 - 8 (6 bit)
access : read-only
TGW : Transmit Gateway Buffer indication
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
not transmission from Gateway
#1 : 1
transmission from Gateway
End of enumeration elements list.
TMTS : Transmit Timestamp
bits : 16 - 30 (15 bit)
access : read-only
Channel %s TX History List Access Registers 1
address_offset : 0x800C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Transmit ID
bits : 0 - 14 (15 bit)
access : read-only
TIFL : Transmit Information Label
bits : 16 - 16 (1 bit)
access : read-only
Global Configuration Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPRI : Transmission Priority
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
ID Priority
#1 : 1
Message Buffer Number Priority
End of enumeration elements list.
DCE : DLC Check Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
DLC check disabled
#1 : 1
DLC check enabled
End of enumeration elements list.
DRE : DLC Replacement Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DLC replacement disabled
#1 : 1
DLC replacement enabled
End of enumeration elements list.
MME : Mirror Mode Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Mirror Mode disabled
#1 : 1
Mirror Mode enabled
End of enumeration elements list.
DCS : Data Link Controller Clock Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Internal clean clock
#1 : 1
External Clock source connected to CANMCLK pin
End of enumeration elements list.
CMPOC : CAN-FD message Payload overflow configuration
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Message is rejected
#1 : 1
Message payload is cut to fit to configured message size
End of enumeration elements list.
TSP : Timestamp Prescaler
bits : 8 - 10 (3 bit)
access : read-write
TSSS : Timestamp Source Select
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Source clock for Timestamp counter is peripheral clock
#1 : 1
Source clock for Timestamp counter is bit time clock
End of enumeration elements list.
TSBTCS : Timestamp Bit Time Channel Select
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
select clock from Channel 0
#001 : 001
select clock from Channel 1
: Others
Setting prohibited
End of enumeration elements list.
ITRCP : Interval Timer Reference Clock Prescaler
bits : 16 - 30 (15 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x840C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x841C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x842C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x843C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x844C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x845C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x846C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x847C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x848C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x8498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x849C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
RAM Test Page Access Registers %s
address_offset : 0x84FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDTA : RAM Data Test Access
bits : 0 - 30 (31 bit)
access : read-write
Global Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GMDC : Global Mode Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Global Operation Mode Request
#01 : 01
Global Reset Mode Request
#10 : 10
Global Halt Mode Request
#11 : 11
Keep Current Value
End of enumeration elements list.
GSLPR : Global Sleep Request
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Global Sleep Request Disabled
#1 : 1
Global Sleep Request Enabled
End of enumeration elements list.
DEIE : DLC check Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
DLC check Interrupt Disabled
#1 : 1
DLC check Interrupt Enabled
End of enumeration elements list.
MEIE : Message lost Error Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Message Lost Error Interrupt Disabled
#1 : 1
Message Lost Error Interrupt Enabled
End of enumeration elements list.
THLEIE : TX History List Entry Lost Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
TX History List Entry Lost Interrupt Disabled
#1 : 1
TX History List Entry Lost Interrupt Enabled
End of enumeration elements list.
CMPOFIE : CAN-FD message payload overflow Flag Interrupt enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
CAN-FD message payload overflow Flag Interrupt Disabled
#1 : 1
CAN-FD message payload overflow Flag Interrupt Enabled
End of enumeration elements list.
QMEIE : TXQ Message lost Error Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
TXQ Message Lost Error Interrupt Disabled
#1 : 1
TXQ Message Lost Error Interrupt Enabled
End of enumeration elements list.
MOWEIE : GW FIFO Message overwrite Error Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
GW FIFO Message overwrite Error Interrupt Disabled
#1 : 1
GW FIFO Message overwrite Error Interrupt Enabled
End of enumeration elements list.
TSRST : Timestamp Reset
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Timestamp not reset
#1 : 1
Timestamp reset
End of enumeration elements list.
TSWR : Timestamp Write
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Timestamp write disabled
#1 : 1
Timestamp write enabled
End of enumeration elements list.
Global Status Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GRSTSTS : Global Reset Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Not in Reset Mode
#1 : 1
In Reset Mode
End of enumeration elements list.
GHLTSTS : Global Halt Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Not in Halt Mode
#1 : 1
In Halt Mode
End of enumeration elements list.
GSLPSTS : Global Sleep Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Not in Sleep Mode
#1 : 1
In Sleep Mode
End of enumeration elements list.
GRAMINIT : Global RAM Initialisation
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
RAM initialisation is finished
#1 : 1
RAM initialisation ongoing
End of enumeration elements list.
Global Error Flag Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEF : DLC Error Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DLC Error not detected
#1 : 1
DLC Error detected
End of enumeration elements list.
MES : Message Lost Error Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Message lost Error not detected
#1 : 1
Message lost Error detected
End of enumeration elements list.
THLES : TX History List Entry Lost Error Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
TX History List Entry Lost Error not detected
#1 : 1
TX History List Entry Lost Error detected
End of enumeration elements list.
CMPOF : CAN-FD message payload overflow Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
CAN-FD message payload overflow not detected
#1 : 1
CAN-FD message payload overflow detected
End of enumeration elements list.
QOWES : TXQ Message overwrite Error Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
TXQ Message overwrite Error not detected
#1 : 1
TXQ Message overwrite Error detected
End of enumeration elements list.
OTBMLTSTS : OTB FIFO Message Lost Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Message lost Error not detected
#1 : 1
Message lost Error detected
End of enumeration elements list.
QMES : TXQ Message Lost Error Status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
TXQ Message lost Error not detected
#1 : 1
TXQ Message lost Error detected
End of enumeration elements list.
RXSFAIL0 : RX Scan Fail of Channel 0
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX Scan fail not detected
#1 : 1
RX Scan fail detected
End of enumeration elements list.
RXSFAIL1 : RX Scan Fail of Channel 1
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
RX Scan fail not detected
#1 : 1
RX Scan fail detected
End of enumeration elements list.
EEF0 : ECC Error Flag for Channel 0
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
ECC Error not detected during TX-SCAN
#1 : 1
ECC Error detected during TX-SCAN
End of enumeration elements list.
EEF1 : ECC Error Flag for Channel 1
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
ECC Error not detected during TX-SCAN
#1 : 1
ECC Error detected during TX-SCAN
End of enumeration elements list.
Global Timestamp Counter Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS : Timestamp Value
bits : 0 - 14 (15 bit)
access : read-only
Global Acceptance Filter List Entry Control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFLPN : Acceptance Filter List Page Number
bits : 0 - 2 (3 bit)
access : read-write
AFLDAE : Acceptance Filter List Data Access Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Acceptance Filter List Data access disabled
#1 : 1
Acceptance Filter List Data access enabled
End of enumeration elements list.
Global Acceptance Filter List Configuration Register 0
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNC1 : Rule Number for Channel 1
bits : 0 - 7 (8 bit)
access : read-write
RNC0 : Rule Number for Channel 0
bits : 16 - 23 (8 bit)
access : read-write
RX Message Buffer Number Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NRXMB : Number of RX Message Buffers
bits : 0 - 6 (7 bit)
access : read-write
RMPLS : Reception Message Buffer Payload Data Size
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RX Message Buffer New Data Register 0
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMNSu : RX Message Buffer New Data Status
bits : 0 - 30 (31 bit)
access : read-write
Enumeration:
#0 : 0
New Data not stored in corresponding RX Message Buffer
#1 : 1
New Data stored in corresponding RX Message Buffer
End of enumeration elements list.
Channel %s Error Flag Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BEF : Bus Error Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bus Error not detected
#1 : 1
Channel Bus Error detected
End of enumeration elements list.
EWF : Error Warning Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Error Warning not detected
#1 : 1
Channel Error Warning detected
End of enumeration elements list.
EPF : Error Passive Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Error Passive not detected
#1 : 1
Channel Error Passive detected
End of enumeration elements list.
BOEF : Bus-Off Entry Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bus-Off Entry not detected
#1 : 1
Channel Bus-Off Entry detected
End of enumeration elements list.
BORF : Bus-Off Recovery Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bus-Off Recovery not detected
#1 : 1
Channel Bus-Off Recovery detected
End of enumeration elements list.
OVLF : Overload Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Overload not detected
#1 : 1
Channel Overload detected
End of enumeration elements list.
BLF : Bus Lock Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bus Lock not detected
#1 : 1
Channel Bus Lock detected
End of enumeration elements list.
ALF : Arbitration Lost Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Arbitration Lost not detected
#1 : 1
Channel Arbitration Lost detected
End of enumeration elements list.
SERR : Stuff Error
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel stuff Error not detected
#1 : 1
Channel stuff Error detected
End of enumeration elements list.
FERR : Form Error
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Form Error not detected
#1 : 1
Channel Form Error detected
End of enumeration elements list.
AERR : Acknowledge Error
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Ack Error not detected
#1 : 1
Channel Ack Error detected
End of enumeration elements list.
CERR : CRC Error
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel CRC Error not detected
#1 : 1
Channel CRC Error detected
End of enumeration elements list.
B1ERR : Bit 1 Error
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bit 1 Error not detected
#1 : 1
Channel Bit 1 Error detected
End of enumeration elements list.
B0ERR : Bit 0 Error
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Bit 0 Error not detected
#1 : 1
Channel Bit 0 Error detected
End of enumeration elements list.
ADERR : Acknowledge Delimiter Error
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Channel Ack Del Error not detected
#1 : 1
Channel Ack Del Error detected
End of enumeration elements list.
CRCREG : CRC Register value
bits : 16 - 29 (14 bit)
access : read-only
RX FIFO Configuration / Control Registers %s
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RX FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
RFIE : RX FIFO Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RFPLS : Rx FIFO Payload Data Size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RFDC : RX FIFO Depth Configuration
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
RFIM : RX FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
#1 : 1
Interrupt generated at the end of every received message storage
End of enumeration elements list.
RFIGCV : RX FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
RFFIE : RX FIFO Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RX FIFO Configuration / Control Registers %s
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RX FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
RFIE : RX FIFO Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RFPLS : Rx FIFO Payload Data Size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RFDC : RX FIFO Depth Configuration
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
RFIM : RX FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
#1 : 1
Interrupt generated at the end of every received message storage
End of enumeration elements list.
RFIGCV : RX FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
RFFIE : RX FIFO Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RX FIFO Configuration / Control Registers %s
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RX FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
RFIE : RX FIFO Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RFPLS : Rx FIFO Payload Data Size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RFDC : RX FIFO Depth Configuration
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
RFIM : RX FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
#1 : 1
Interrupt generated at the end of every received message storage
End of enumeration elements list.
RFIGCV : RX FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
RFFIE : RX FIFO Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RX FIFO Configuration / Control Registers %s
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RX FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
RFIE : RX FIFO Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RFPLS : Rx FIFO Payload Data Size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RFDC : RX FIFO Depth Configuration
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
RFIM : RX FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
#1 : 1
Interrupt generated at the end of every received message storage
End of enumeration elements list.
RFIGCV : RX FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
RFFIE : RX FIFO Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
TX Message Buffer Transmission Request Status Register %s
address_offset : 0xCD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTRSTSg : TX Message Buffer Transmission Request Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not requested for corresponding TX Message Buffer
#1 : 1
Transmission requested for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Request Status Register %s
address_offset : 0xCD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTRSTSg : TX Message Buffer Transmission Request Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not requested for corresponding TX Message Buffer
#1 : 1
Transmission requested for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Request Status Register %s
address_offset : 0xCD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTRSTSg : TX Message Buffer Transmission Request Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not requested for corresponding TX Message Buffer
#1 : 1
Transmission requested for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Request Status Register %s
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTRSTSg : TX Message Buffer Transmission Request Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not requested for corresponding TX Message Buffer
#1 : 1
Transmission requested for corresponding TX Message Buffer
End of enumeration elements list.
RX FIFO Configuration / Control Registers %s
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RX FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
RFIE : RX FIFO Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RFPLS : Rx FIFO Payload Data Size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RFDC : RX FIFO Depth Configuration
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
RFIM : RX FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
#1 : 1
Interrupt generated at the end of every received message storage
End of enumeration elements list.
RFIGCV : RX FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
RFFIE : RX FIFO Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RX FIFO Configuration / Control Registers %s
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RX FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
RFIE : RX FIFO Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RFPLS : Rx FIFO Payload Data Size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RFDC : RX FIFO Depth Configuration
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
RFIM : RX FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
#1 : 1
Interrupt generated at the end of every received message storage
End of enumeration elements list.
RFIGCV : RX FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
RFFIE : RX FIFO Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
TX Message Buffer Transmission Abort Request Status Register %s
address_offset : 0xD70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTARSTSg : TX Message Buffer Transmission abort Request Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission abort not requested for corresponding TX Message Buffer
#1 : 1
Transmission abort requested for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Abort Request Status Register %s
address_offset : 0xD74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTARSTSg : TX Message Buffer Transmission abort Request Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission abort not requested for corresponding TX Message Buffer
#1 : 1
Transmission abort requested for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Abort Request Status Register %s
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTARSTSg : TX Message Buffer Transmission abort Request Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission abort not requested for corresponding TX Message Buffer
#1 : 1
Transmission abort requested for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Abort Request Status Register %s
address_offset : 0xD7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTARSTSg : TX Message Buffer Transmission abort Request Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission abort not requested for corresponding TX Message Buffer
#1 : 1
Transmission abort requested for corresponding TX Message Buffer
End of enumeration elements list.
RX FIFO Configuration / Control Registers %s
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RX FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
RFIE : RX FIFO Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RFPLS : Rx FIFO Payload Data Size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RFDC : RX FIFO Depth Configuration
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
RFIM : RX FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
#1 : 1
Interrupt generated at the end of every received message storage
End of enumeration elements list.
RFIGCV : RX FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
RFFIE : RX FIFO Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RX FIFO Configuration / Control Registers %s
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RX FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO disabled
#1 : 1
FIFO enabled
End of enumeration elements list.
RFIE : RX FIFO Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RFPLS : Rx FIFO Payload Data Size configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 Bytes
#001 : 001
12 Bytes
#010 : 010
16 Bytes
#011 : 011
20 Bytes
#100 : 100
24 Bytes
#101 : 101
32 Bytes
#110 : 110
48 Bytes
#111 : 111
64 Bytes
End of enumeration elements list.
RFDC : RX FIFO Depth Configuration
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
FIFO Depth = 0 Messages
#001 : 001
FIFO Depth = 4 Messages
#010 : 010
FIFO Depth = 8 Messages
#011 : 011
FIFO Depth = 16 Messages
#100 : 100
FIFO Depth = 32 Messages
#101 : 101
FIFO Depth = 48 Messages
#110 : 110
FIFO Depth = 64 Messages
#111 : 111
FIFO Depth = 128 Messages
End of enumeration elements list.
RFIM : RX FIFO Interrupt Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
#1 : 1
Interrupt generated at the end of every received message storage
End of enumeration elements list.
RFIGCV : RX FIFO Interrupt Generation Counter Value
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : 000
Interrupt generated when FIFO is 1/8th Full
#001 : 001
Interrupt generated when FIFO is 1/4th Full
#010 : 010
Interrupt generated when FIFO is 3/8th Full
#011 : 011
Interrupt generated when FIFO is 1/2 Full
#100 : 100
Interrupt generated when FIFO is 5/8th Full
#101 : 101
Interrupt generated when FIFO is 3/4th Full
#110 : 110
Interrupt generated when FIFO is 7/8th Full
#111 : 111
Interrupt generated when FIFO is Full
End of enumeration elements list.
RFFIE : RX FIFO Full interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt generation disabled
#1 : 1
FIFO Interrupt generation enabled
End of enumeration elements list.
RX FIFO Status Registers %s
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEMP : RX FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
RFFLL : RX FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
RFMLT : RX FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
RFIF : RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied
#1 : 1
FIFO Interrupt condition satisfied
End of enumeration elements list.
RFMC : RX FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
RFFIF : RX FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Full interrupt condition not satisfied
#1 : 1
FIFO Full interrupt condition satisfied
End of enumeration elements list.
TX Message Buffer Transmission Completion Status Register %s
address_offset : 0xE10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTCSTSg : TX Message Buffer Transmission Completion Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not complete for corresponding TX Message Buffer
#1 : 1
Transmission completed for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Completion Status Register %s
address_offset : 0xE14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTCSTSg : TX Message Buffer Transmission Completion Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not complete for corresponding TX Message Buffer
#1 : 1
Transmission completed for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Completion Status Register %s
address_offset : 0xE18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTCSTSg : TX Message Buffer Transmission Completion Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not complete for corresponding TX Message Buffer
#1 : 1
Transmission completed for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Completion Status Register %s
address_offset : 0xE1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTCSTSg : TX Message Buffer Transmission Completion Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not complete for corresponding TX Message Buffer
#1 : 1
Transmission completed for corresponding TX Message Buffer
End of enumeration elements list.
RX FIFO Status Registers %s
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEMP : RX FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
RFFLL : RX FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
RFMLT : RX FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
RFIF : RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied
#1 : 1
FIFO Interrupt condition satisfied
End of enumeration elements list.
RFMC : RX FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
RFFIF : RX FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Full interrupt condition not satisfied
#1 : 1
FIFO Full interrupt condition satisfied
End of enumeration elements list.
RX FIFO Status Registers %s
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEMP : RX FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
RFFLL : RX FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
RFMLT : RX FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
RFIF : RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied
#1 : 1
FIFO Interrupt condition satisfied
End of enumeration elements list.
RFMC : RX FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
RFFIF : RX FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Full interrupt condition not satisfied
#1 : 1
FIFO Full interrupt condition satisfied
End of enumeration elements list.
TX Message Buffer Transmission Abort Status Register %s
address_offset : 0xEB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTASTSg : TX Message Buffer Transmission abort Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not aborted for corresponding TX Message Buffer
#1 : 1
Transmission aborted for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Abort Status Register %s
address_offset : 0xEB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTASTSg : TX Message Buffer Transmission abort Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not aborted for corresponding TX Message Buffer
#1 : 1
Transmission aborted for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Abort Status Register %s
address_offset : 0xEB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTASTSg : TX Message Buffer Transmission abort Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not aborted for corresponding TX Message Buffer
#1 : 1
Transmission aborted for corresponding TX Message Buffer
End of enumeration elements list.
TX Message Buffer Transmission Abort Status Register %s
address_offset : 0xEBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFDTMTASTSg : TX Message Buffer Transmission abort Status
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#0 : 0
Transmission not aborted for corresponding TX Message Buffer
#1 : 1
Transmission aborted for corresponding TX Message Buffer
End of enumeration elements list.
RX FIFO Status Registers %s
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEMP : RX FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
RFFLL : RX FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
RFMLT : RX FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
RFIF : RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied
#1 : 1
FIFO Interrupt condition satisfied
End of enumeration elements list.
RFMC : RX FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
RFFIF : RX FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Full interrupt condition not satisfied
#1 : 1
FIFO Full interrupt condition satisfied
End of enumeration elements list.
RX FIFO Status Registers %s
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEMP : RX FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
RFFLL : RX FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
RFMLT : RX FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
RFIF : RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied
#1 : 1
FIFO Interrupt condition satisfied
End of enumeration elements list.
RFMC : RX FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
RFFIF : RX FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Full interrupt condition not satisfied
#1 : 1
FIFO Full interrupt condition satisfied
End of enumeration elements list.
RX FIFO Status Registers %s
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEMP : RX FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
RFFLL : RX FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
RFMLT : RX FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
RFIF : RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied
#1 : 1
FIFO Interrupt condition satisfied
End of enumeration elements list.
RFMC : RX FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
RFFIF : RX FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Full interrupt condition not satisfied
#1 : 1
FIFO Full interrupt condition satisfied
End of enumeration elements list.
TX Message Buffer Interrupt Enable Configuration Register %s
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMIEg : TX Message Buffer Interrupt Enable
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Interrupt disabled for corresponding TX message buffer
#1 : 1
TX Message Buffer Interrupt enabled for corresponding TX message buffer
End of enumeration elements list.
TX Message Buffer Interrupt Enable Configuration Register %s
address_offset : 0xF54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMIEg : TX Message Buffer Interrupt Enable
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Interrupt disabled for corresponding TX message buffer
#1 : 1
TX Message Buffer Interrupt enabled for corresponding TX message buffer
End of enumeration elements list.
TX Message Buffer Interrupt Enable Configuration Register %s
address_offset : 0xF58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMIEg : TX Message Buffer Interrupt Enable
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Interrupt disabled for corresponding TX message buffer
#1 : 1
TX Message Buffer Interrupt enabled for corresponding TX message buffer
End of enumeration elements list.
TX Message Buffer Interrupt Enable Configuration Register %s
address_offset : 0xF5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMIEg : TX Message Buffer Interrupt Enable
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
#0 : 0
TX Message Buffer Interrupt disabled for corresponding TX message buffer
#1 : 1
TX Message Buffer Interrupt enabled for corresponding TX message buffer
End of enumeration elements list.
RX FIFO Status Registers %s
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEMP : RX FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
RFFLL : RX FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
RFMLT : RX FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
RFIF : RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied
#1 : 1
FIFO Interrupt condition satisfied
End of enumeration elements list.
RFMC : RX FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
RFFIF : RX FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Full interrupt condition not satisfied
#1 : 1
FIFO Full interrupt condition satisfied
End of enumeration elements list.
RX FIFO Status Registers %s
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEMP : RX FIFO Empty
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Empty
#1 : 1
FIFO Empty
End of enumeration elements list.
RFFLL : RX FIFO Full
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO Not Full
#1 : 1
FIFO Full
End of enumeration elements list.
RFMLT : RX FIFO Message Lost
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Message Lost in FIFO
#1 : 1
FIFO Message Lost
End of enumeration elements list.
RFIF : RX FIFO Interrupt Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Interrupt condition not satisfied
#1 : 1
FIFO Interrupt condition satisfied
End of enumeration elements list.
RFMC : RX FIFO Message Count
bits : 8 - 14 (7 bit)
access : read-only
RFFIF : RX FIFO Full Interrupt Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Full interrupt condition not satisfied
#1 : 1
FIFO Full interrupt condition satisfied
End of enumeration elements list.
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