USBHS

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 30 (31 bit)
access : read-write

CFIFOL

FIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0

CFIFOLL

FIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0

BCCTRL

Battery Charging Control Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDPSRCE : IDPSRC Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable IDP_SRC circuit

#1 : 1

Enable IDP_SRC circuit

End of enumeration elements list.

IDMSINKE : IDMSINK Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable IDM_SINK circuit

#1 : 1

Enable IDM_SINK circuit

End of enumeration elements list.

VDPSRCE : VDPSRC Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable VDP_SRC circuit

#1 : 1

Enable VDP_SRC circuit

End of enumeration elements list.

IDPSINKE : IDPSINK Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable IDP_SINK circuit

#1 : 1

Enable IDP_SINK circuit

End of enumeration elements list.

VDMSRCE : VDMSRC Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable VDM_SRC circuit

#1 : 1

Enable VDM_SRC circuit

End of enumeration elements list.

DCPMODE : DCP Mode Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable RDCP_DAT resistor

#1 : 1

Enable RDCP_DAT resistor

End of enumeration elements list.

CHGDETSTS : CHGDET Status Flag
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

The CHGDET pin is at low level

#1 : 1

The CHGDET pin is at high level

End of enumeration elements list.

PDDETSTS : PDDET Status Flag
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : 0

The PDDET pin is at low level

#1 : 1

The PDDET pin is at high level

End of enumeration elements list.

PL1CTRL1

Function L1 Control Register 1
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1RESPEN : L1 Response Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not support LPM

#1 : 1

Support LPM

End of enumeration elements list.

L1RESPMD : L1 Response Mode
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#00 : 00

NYET response

#01 : 01

ACK response

#10 : 10

STALL response

#11 : 11

Response based on L1NEGOMD setting

End of enumeration elements list.

L1NEGOMD : L1 Response Negotiation Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Return ACK when received HIRD is larger than HIRDTHR[3:0]. Otherwise (including when HIRD = HIRDTHR[3:0]), return NYET

#1 : 1

Return ACK when received HIRD is smaller than HIRDTHR[3:0]. Otherwise (including when HIRD = HIRDTHR[3:0]), return NYET

End of enumeration elements list.

DVSQ : DVSQ Extension Flag
bits : 4 - 6 (3 bit)
access : read-only

Enumeration:

#0000 : 0000

Powered state

#0001 : 0001

Default state

#0010 : 0010

Address state

#0011 : 0011

Configured state

#01xx : 01xx

Suspend state

#10xx : 10xx

L1 state

End of enumeration elements list.

HIRDTHR : L1 Response Negotiation Threshold Value
bits : 8 - 10 (3 bit)
access : read-write

L1EXTMD : PHY Control Mode at L1 Return
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not set LPSTS.SUSPENDM bit through hardware when Host K is received

#1 : 1

Set LPSTS.SUSPENDM bit through hardware when Host K is received

End of enumeration elements list.

PL1CTRL2

Function L1 Control Register 2
address_offset : 0x146 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIRDMON : HIRD Value Monitor
bits : 8 - 10 (3 bit)
access : read-only

RWEMON : RWE Value Monitor
bits : 12 - 11 (0 bit)
access : read-only

HL1CTRL1

Host L1 Control Register 1
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1REQ : L1 Transition Request
bits : 0 - -1 (0 bit)
access : read-write

L1STATUS : L1 Request Completion Status
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#00 : 00

ACK received

#01 : 01

NYET received

#10 : 10

STALL received

#11 : 11

Transaction error

End of enumeration elements list.

HL1CTRL2

Host L1 Control Register 2
address_offset : 0x14A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1ADDR : LPM Token DeviceAddress
bits : 0 - 2 (3 bit)
access : read-write

HIRD : LPM Token HIRD
bits : 8 - 10 (3 bit)
access : read-write

L1RWE : LPM Token L1 RemoteWake Enable
bits : 12 - 11 (0 bit)
access : read-write

BESL : BESL and Alternate HIRD
bits : 15 - 14 (0 bit)
access : read-write

CFIFOH

FIFO Port Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write

DPUSR0R

Deep Software Standby USB Transceiver Control/Pin Monitor Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DOVCAHM : OVRCURA Input Flag
bits : 20 - 19 (0 bit)
access : read-only

DOVCBHM : OVRCURB Input Flag
bits : 21 - 20 (0 bit)
access : read-only

DVBSTSHM : VBUS Input Flag
bits : 23 - 22 (0 bit)
access : read-only

DPUSR1R

Deep Software Standby USB Suspend/Resume Interrupt Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOVCAHE : OVRCURA Interrupt Enable Clear
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable recovery from Deep Software Standby mode

#1 : 1

Enable recovery from Deep Software Standby mode

End of enumeration elements list.

DOVCBHE : OVRCURB Interrupt Enable Clear
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable recovery from Deep Software Standby mode

#1 : 1

Enable recovery from Deep Software Standby mode

End of enumeration elements list.

DVBSTSHE : VBUS Interrupt Enable/Clear
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable recovery from Deep Software Standby mode

#1 : 1

Enable recovery from Deep Software Standby mode

End of enumeration elements list.

DOVCAH : OVRCURA Interrupt Source Return Status Flag
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

#0 : 0

System has not recovered from Deep Software Standby mode

#1 : 1

System recovered from Deep Software Standby mode

End of enumeration elements list.

DOVCBH : OVRCURB Interrupt Source Return Status Flag
bits : 21 - 20 (0 bit)
access : read-only

Enumeration:

#0 : 0

System has not recovered from Deep Software Standby mode

#1 : 1

System recovered from Deep Software Standby mode

End of enumeration elements list.

DVBSTSH : VBUS Interrupt Source Return Status Flag
bits : 23 - 22 (0 bit)
access : read-only

Enumeration:

#0 : 0

System has not recovered from Deep Software Standby mode

#1 : 1

System recovered from Deep Software Standby mode

End of enumeration elements list.

DPUSR2R

Deep Software Standby USB Suspend/Resume Interrupt Register
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPINT : Indication of Return from DP Interrupt Source
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

System has not recovered from Deep Software Standby mode

#1 : 1

System recovered from Deep Software Standby mode

End of enumeration elements list.

DMINT : Indication of Return from DM Interrupt Source
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

System has not recovered from Deep Software Standby mode

#1 : 1

System recovered from Deep Software Standby mode

End of enumeration elements list.

DPVAL : DP Input
bits : 4 - 3 (0 bit)
access : read-only

DMVAL : DM Input
bits : 5 - 4 (0 bit)
access : read-only

DPINTE : DP Interrupt Enable Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable recovery from Deep Software Standby mode

#1 : 1

Enable recovery from Deep Software Standby mode

End of enumeration elements list.

DMINTE : DM Interrupt Enable Clear
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable recovery from Deep Software Standby mode

#1 : 1

Enable recovery from Deep Software Standby mode

End of enumeration elements list.

DPUSRCR

Deep Software Standby USB Suspend/Resume Command Register
address_offset : 0x16A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIXPHY : USB Transceiver Control Fix
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Invoke/recover from Deep Software Standby mode

End of enumeration elements list.

FIXPHYPD : USB Transceiver Control Fix for PLL
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Invoke/recover from Deep Software Standby mode

End of enumeration elements list.

CFIFOHH

FIFO Port Register
address_offset : 0x17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 6 (7 bit)
access : read-write

D0FIFO

FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 30 (31 bit)
access : read-write

D1FIFO

FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 30 (31 bit)
access : read-write

D0FIFOL

FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

D1FIFOL

FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

D0FIFOLL

FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

D1FIFOLL

FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

D0FIFOH

FIFO Port Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write

D1FIFOH

FIFO Port Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFOH
reset_Mask : 0x0

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write

D0FIFOHH

FIFO Port Register
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 6 (7 bit)
access : read-write

D1FIFOHH

FIFO Port Register
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFOHH
reset_Mask : 0x0

FIFOPORT : Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 6 (7 bit)
access : read-write

BUSWAIT

CPU Bus Wait Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWAIT : CPU Bus Access Wait Specification
bits : 0 - 2 (3 bit)
access : read-write

CFIFOSEL

CFIFO Port Selection Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

DCP (default control pipe)

0x1 : 0x1

Pipe 1

0x2 : 0x2

Pipe 2

0x3 : 0x3

Pipe 3

0x4 : 0x4

Pipe 4

0x5 : 0x5

Pipe 5

0x6 : 0x6

Pipe 6

0x7 : 0x7

Pipe 7

0x8 : 0x8

Pipe 8

0x9 : 0x9

Pipe 9

: Others

Setting prohibited

End of enumeration elements list.

ISEL : FIFO Port Access Direction when DCP Is Selected
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select reading from the FIFO buffer

#1 : 1

Select writing to the FIFO buffer

End of enumeration elements list.

BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little endian

#1 : 1

Big endian

End of enumeration elements list.

MBW : CFIFO Port Access Bit Width
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : 00

8-bit width

#01 : 01

16-bit width

#10 : 10

32-bit width

#11 : 11

Setting prohibited

End of enumeration elements list.

REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : 0

Do not rewind buffer pointer (Writing 0 has no effect.)

#1 : 1

Rewind buffer pointer

End of enumeration elements list.

RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Clear DTLN[11:0] flags in the FIFO port control register to 000h when all receive data is read from CFIFO

#1 : 1

Decrement DTLN[11:0] flags each time receive data is read from CFIFO

End of enumeration elements list.

CFIFOCTR

FIFO Port Control Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTLN : Receive Data Length Flag
bits : 0 - 10 (11 bit)
access : read-only

FRDY : FIFO Port Ready Flag
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : 0

FIFO port access disabled

#1 : 1

FIFO port access enabled

End of enumeration elements list.

BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : 0

No operation (writing 0 has no effect)

#1 : 1

Clear FIFO buffer on the CPU side

End of enumeration elements list.

BVAL : FIFO Buffer Valid Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Writing ended

End of enumeration elements list.

D0FIFOSEL

D%sFIFO Port Selection Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No pipe specification

0x1 : 0x1

Pipe 1

0x2 : 0x2

Pipe 2

0x3 : 0x3

Pipe 3

0x4 : 0x4

Pipe 4

0x5 : 0x5

Pipe 5

0x6 : 0x6

Pipe 6

0x7 : 0x7

Pipe 7

0x8 : 0x8

Pipe 8

0x9 : 0x9

Pipe 9

: Others

Setting prohibited

End of enumeration elements list.

BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little endian

#1 : 1

Big endian

End of enumeration elements list.

MBW : FIFO Port Access Bit Width
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : 00

8-bit width

#01 : 01

16-bit width

#10 : 10

32-bit width

#11 : 11

Setting prohibited

End of enumeration elements list.

DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable DMA/DTC transfer request

#1 : 1

Enable DMA/DTC transfer request

End of enumeration elements list.

DCLRM : Auto FIFO Buffer Clear Mode after Specified Pipe is Read
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto buffer clear mode

#1 : 1

Enable auto buffer clear mode

End of enumeration elements list.

REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : 0

Do not rewind buffer pointer (writing 0 has no effect)

#1 : 1

Rewind buffer pointer

End of enumeration elements list.

RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Clear DTLN[11:0] flags in the FIFO port control register to 000h when all receive data is read from DnFIFO (after read of a single plane in double buffer mode)

#1 : 1

Decrement DTLN[11:0] flags each time receive data is read from DnFIFO

End of enumeration elements list.

D0FIFOCTR

FIFO Port Control Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTLN : Receive Data Length Flag
bits : 0 - 10 (11 bit)
access : read-only

FRDY : FIFO Port Ready Flag
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : 0

FIFO port access disabled

#1 : 1

FIFO port access enabled

End of enumeration elements list.

BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : 0

No operation (writing 0 has no effect)

#1 : 1

Clear FIFO buffer on the CPU side

End of enumeration elements list.

BVAL : FIFO Buffer Valid Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Writing ended

End of enumeration elements list.

D1FIFOSEL

D%sFIFO Port Selection Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No pipe specification

0x1 : 0x1

Pipe 1

0x2 : 0x2

Pipe 2

0x3 : 0x3

Pipe 3

0x4 : 0x4

Pipe 4

0x5 : 0x5

Pipe 5

0x6 : 0x6

Pipe 6

0x7 : 0x7

Pipe 7

0x8 : 0x8

Pipe 8

0x9 : 0x9

Pipe 9

: Others

Setting prohibited

End of enumeration elements list.

BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little endian

#1 : 1

Big endian

End of enumeration elements list.

MBW : FIFO Port Access Bit Width
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : 00

8-bit width

#01 : 01

16-bit width

#10 : 10

32-bit width

#11 : 11

Setting prohibited

End of enumeration elements list.

DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable DMA/DTC transfer request

#1 : 1

Enable DMA/DTC transfer request

End of enumeration elements list.

DCLRM : Auto FIFO Buffer Clear Mode after Specified Pipe is Read
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto buffer clear mode

#1 : 1

Enable auto buffer clear mode

End of enumeration elements list.

REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : 0

Do not rewind buffer pointer (writing 0 has no effect)

#1 : 1

Rewind buffer pointer

End of enumeration elements list.

RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Clear DTLN[11:0] flags in the FIFO port control register to 000h when all receive data is read from DnFIFO (after read of a single plane in double buffer mode)

#1 : 1

Decrement DTLN[11:0] flags each time receive data is read from DnFIFO

End of enumeration elements list.

D1FIFOCTR

FIFO Port Control Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTLN : Receive Data Length Flag
bits : 0 - 10 (11 bit)
access : read-only

FRDY : FIFO Port Ready Flag
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : 0

FIFO port access disabled

#1 : 1

FIFO port access enabled

End of enumeration elements list.

BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : 0

No operation (writing 0 has no effect)

#1 : 1

Clear FIFO buffer on the CPU side

End of enumeration elements list.

BVAL : FIFO Buffer Valid Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Writing ended

End of enumeration elements list.

INTENB0

Interrupt Enable Register 0
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRDYE : Buffer Ready Interrupt Request Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

NRDYE : Buffer Not Ready Response Interrupt Request Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

BEMPE : Buffer Empty Interrupt Request Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

CTRE : Control Transfer Stage Transition Interrupt Request Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

DVSE : Device State Transition Interrupt Request Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

SOFE : Frame Number Update Interrupt Request Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

RSME : Resume Interrupt Request Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

VBSE : VBUS Interrupt Request Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

INTENB1

Interrupt Enable Register 1
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDDETINTE : PDDETINT Detection Interrupt Request Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

SACKE : Setup Transaction Normal Response Interrupt Request Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

SIGNE : Setup Transaction Error Interrupt Request Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

EOFERRE : EOF Error Detection Interrupt Request Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

LPMENDE : LPM Transaction End Interrupt Request Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

L1RSMENDE : L1 Resume End Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

ATTCHE : Connection Detection Interrupt Request Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

DTCHE : Disconnection Detection Interrupt Request Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

BCHGE : USB Bus Change Interrupt Request Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

OVRCRE : OVRCRE Interrupt Request Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

BRDYENB

BRDY Interrupt Enable Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPEBRDYE : BRDY Interrupt Request Enable for Pipes [9:0]
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

NRDYENB

NRDY Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPENRDYE : NRDY Interrupt Enable for Pipes [9:0]
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

BEMPENB

BEMP Interrupt Enable Register
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPEBEMPE : BEMP Interrupt Enable for Pipes [9:0]
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt request

#1 : 1

Enable interrupt request

End of enumeration elements list.

SOFCFG

SOF Output Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EDGESTS : Interrupt Edge Processing Status Flag
bits : 4 - 3 (0 bit)
access : read-only

INTL : Interrupt Output Sense Select
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Edge detection

#1 : 1

Level detection

End of enumeration elements list.

BRDYM : PIPEBRDY Interrupt Status Clear Timing
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Clear BRDY flag through software

#1 : 1

Clear BRDY flag by the USBHS through a data read from the FIFO buffer or data write to the FIFO buffer

End of enumeration elements list.

TRNENSEL : Transaction-Enabled Time Select
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not low-speed communication

#1 : 1

Low-speed communication

End of enumeration elements list.

PHYSET

PHY Setting Register
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRPD : Power-Down Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not enter low power mode

#1 : 1

Enter low power mode

End of enumeration elements list.

PLLRESET : PLL Reset Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable PLL reset control for UTMI_PHY

#1 : 1

Enable PLL reset control for UTMI_PHY

End of enumeration elements list.

CDPEN : Charging Downstream Port Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable downstream port charging

#1 : 1

Enable downstream port charging

End of enumeration elements list.

CLKSEL : Input System Clock Frequency
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

12 MHz

#01 : 01

Setting prohibited

#10 : 10

20 MHz

#11 : 11

24 MHz

End of enumeration elements list.

REPSEL : Terminating Resistance Adjustment Cycle
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : 00

No cycle is set

#01 : 01

Adjust terminating resistance at 16-second intervals

#10 : 10

Adjust terminating resistance at 64-second intervals

#11 : 11

Adjust terminating resistance at 128-second intervals

End of enumeration elements list.

REPSTART : Forcibly Start Terminating Resistance Adjustment
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Force terminating resistance adjustment to start

#1 : 1

Do not force terminating resistance adjustment to start

End of enumeration elements list.

HSEB : CL-only mode
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable CL-only mode

#1 : 1

Enable CL-only mode

End of enumeration elements list.

SYSSTS0

System Configuration Status Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LNST : USB Data Line Status Monitor Flag
bits : 0 - 0 (1 bit)
access : read-only

IDMON : USBHS_ID Pin Monitor Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

USBHS_ID pin is low

#1 : 1

USBHS_ID pin is high

End of enumeration elements list.

SOFEA : SOF Active Monitor Flag While Host Controller Operation Is Selected
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

SOF output stopped

#1 : 1

SOF output operating

End of enumeration elements list.

HTACT : Host Sequencer Status Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

Host sequencer stopped

#1 : 1

Host sequencer operating

End of enumeration elements list.

OVCMON : External USBHS_OVRCURA/USBHS_O VRCURB Input Pin Monitor Flag
bits : 14 - 14 (1 bit)
access : read-only

INTSTS0

Interrupt Status Register 0
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSQ : Control Transfer Stage Flag
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

#000 : 000

Idle or setup stage

#001 : 001

Control read data stage

#010 : 010

Control read status stage

#011 : 011

Control write data stage

#100 : 100

Control write status stage

#101 : 101

Control write (no data) status stage

#110 : 110

Control transfer sequence error

End of enumeration elements list.

VALID : USB Request Reception Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Setup packet not received

#1 : 1

Setup packet received

End of enumeration elements list.

DVSQ : Device State
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

#000 : 000

Powered state

#001 : 001

Default state

#010 : 010

Address state

#011 : 011

Configured state

#1xx : 1xx

Suspend state

End of enumeration elements list.

VBSTS : VBUS Input Status Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

USBHS_VBUS pin is low

#1 : 1

USBHS_VBUS pin is high

End of enumeration elements list.

BRDY : BRDY Interrupt Status Flag
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

No BRDY interrupt occurred

#1 : 1

BRDY interrupt occurred

End of enumeration elements list.

NRDY : NRDY Interrupt Status Flag
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : 0

No NRDY interrupt occurred

#1 : 1

NRDY interrupt occurred

End of enumeration elements list.

BEMP : BEMP Interrupt Status Flag
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : 0

No BEMP interrupt occurred

#1 : 1

BEMP interrupt occurred

End of enumeration elements list.

CTRT : Control Transfer Stage Transition Interrupt Status Flag
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

No control transfer stage transition interrupt occurred

#1 : 1

Control transfer stage transition interrupt occurred

End of enumeration elements list.

DVST : Device State Transition Interrupt Status Flag
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

No device state transition interrupt occurred

#1 : 1

Device state transition interrupt occurred

End of enumeration elements list.

SOFR : Frame Number Refresh Interrupt Status Flag
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

No SOF interrupt occurred

#1 : 1

SOF interrupt occurred

End of enumeration elements list.

RESM : Resume Interrupt Status Flag
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

No resume interrupt occurred

#1 : 1

Resume interrupt occurred

End of enumeration elements list.

VBINT : VBUS Interrupt Status Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

No VBUS interrupt occurred on detecting a change in the USBHS_VBUS pin

#1 : 1

VBUS interrupt occurred on detecting a change in the USBHS_VBUS pin

End of enumeration elements list.

INTSTS1

Interrupt Status Register 1
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDDETINT : PDDET Detection Interrupt Status Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No PDDET interrupt occurred

#1 : 1

PDDET interrupt occurred

End of enumeration elements list.

SACK : Setup Transaction Normal Response Interrupt Status Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No SACK interrupt occurred

#1 : 1

SACK interrupt occurred

End of enumeration elements list.

SIGN : Setup Transaction Error Interrupt Status Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

No SIGN interrupt occurred

#1 : 1

SIGN interrupt occurred

End of enumeration elements list.

EOFERR : EOF Error Detection Interrupt Status Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No EOFERR interrupt occurred

#1 : 1

EOFERR interrupt occurred

End of enumeration elements list.

LPMEND : LPM Transaction End Interrupt Status Flag
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

No LPMEND interrupt occurred

#1 : 1

LPMEND interrupt occurred

End of enumeration elements list.

L1RSMEND : L1 Resume End Interrupt Status Flag
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

No L1RSMEND interrupt occurred

#1 : 1

L1RSMEND interrupt occurred

End of enumeration elements list.

ATTCH : USB Connection Detection Interrupt Status Flag
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

No ATTCH interrupt occurred

#1 : 1

ATTCH interrupt occurred

End of enumeration elements list.

DTCH : USB Disconnection Detection Interrupt Status Flag
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DTCH interrupt occurred

#1 : 1

DTCH interrupt occurred

End of enumeration elements list.

BCHG : USB Bus Change Interrupt Status Flag
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

No BCHG interrupt occurred

#1 : 1

BCHG interrupt occurred

End of enumeration elements list.

OVRCR : OVRCR Interrupt Status Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

No OVRCR interrupt occurred

#1 : 1

OVRCR interrupt occurred

End of enumeration elements list.

BRDYSTS

BRDY Interrupt Status Register
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPEBRDY : BRDY Interrupt Status Flag for Pipe[9:0]
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

#0 : 0

No BRDY interrupt occurred

#1 : 1

BRDY interrupt occurred

End of enumeration elements list.

NRDYSTS

NRDY Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPENRDY : NRDY Interrupt Status Flag for Pipe[9:0]
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

#0 : 0

No NRDY interrupt occurred

#1 : 1

NRDY interrupt occurred.

End of enumeration elements list.

BEMPSTS

BEMP Interrupt Status Register
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPEBEMP : BEMP Interrupt Status Flag for Pipe[9:0]
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

#0 : 0

No BEMP interrupt occurred

#1 : 1

BEMP interrupt occurred.

End of enumeration elements list.

FRMNUM

Frame Number Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRNM : Frame Number Flag
bits : 0 - 9 (10 bit)
access : read-only

CRCE : CRC Error Detection Status Flag
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

OVRN : Overrun/Underrun Detection Status Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred.

End of enumeration elements list.

UFRMNUM

µFrame Number Register
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UFRNM : Microframe number
bits : 0 - 1 (2 bit)
access : read-only

DVCHG : Device State Change
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable writes to the USBADDR.STSRECOV0[2:0] and USBADDR.USBADDR[6:0] bits

#1 : 1

Enable writes to the USBADDR.STSRECOV0[2:0] and USBADDR.USBADDR[6:0] bits

End of enumeration elements list.

USBADDR

USB Address Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBADDR : USB Address Flag
bits : 0 - 5 (6 bit)
access : read-only

STSRECOV0 : Status Recovery
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Reserved

#001 : 001

[D] Return to the full-speed connection and Default state

#010 : 010

[D] Return to the full-speed connection and Address state [H] Return to the low-speed state (bits DVSTCTR0.RHST[2:0] = 001b)

#011 : 011

[D] Return to the full-speed connection and Configured state

#100 : 100

[D] Return to the suspend connection and Suspend state [H] Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)

#101 : 101

[D] Return to the high-speed connection and Default state

#110 : 110

[D] Return to the high-speed connection and Address state [H] Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b)

#111 : 111

[D] Return to the high-speed connection and Configured state

End of enumeration elements list.

USBREQ

USB Request Type Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMREQUESTTYPE : USB request bmRequestType value
bits : 0 - 6 (7 bit)
access : read-write

BREQUEST : USB request bRequest value
bits : 8 - 14 (7 bit)
access : read-write

USBVAL

USB Request Value Register
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WVALUE : USB request wValue value
bits : 0 - 14 (15 bit)
access : read-write

USBINDX

USB Request Index Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WINDEX : USB request wIndex value
bits : 0 - 14 (15 bit)
access : read-write

USBLENG

USB Request Length Register
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WLENTUH : USB request wLength value
bits : 0 - 14 (15 bit)
access : read-write

DCPCFG

DCP Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data receiving direction

#1 : 1

Data transmitting direction

End of enumeration elements list.

SHTNAK : Pipe Blocking on End of Transfer
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Keep pipe open after transfer ends

#1 : 1

Disable pipe after transfer ends

End of enumeration elements list.

CNTMD : Continuous Transfer Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-continuous transfer mode

#1 : 1

Continuous transfer mode

End of enumeration elements list.

DCPMAXP

DCP Maximum Packet Size Register
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPS : Maximum Packet Size
bits : 0 - 5 (6 bit)
access : read-write

DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Address 0x0

0x1 : 0x1

Address 0x1

0x2 : 0x2

Address 0x2

0x3 : 0x3

Address 0x3

0x4 : 0x4

Address 0x4

0x5 : 0x5

Address 0x5

End of enumeration elements list.

PLLSTA

PLL Status Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLLLOCK : PLL Lock Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

PLL not locked

#1 : 1

PLL locked

End of enumeration elements list.

DCPCTR

DCP Control Register
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#10 : 10

STALL response

End of enumeration elements list.

CCPL : Control Transfer End Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable control transfer completion

#1 : 1

Enable control transfer completion

End of enumeration elements list.

PINGE : PING Token Issue Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable PING token

#1 : 1

Enable normal PING operation

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

DCP not used for the USB bus

#1 : 1

DCP in use for the USB bus

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

SUREQCLR : SUREQ Bit Clear
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear SUREQ to 0

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress

#1 : 1

Complete-split (CSPLIT) transaction in progress

End of enumeration elements list.

CSCLR : CSSTS Status Flag Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

(writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

SUREQ : SETUP Token Transmission
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Transmit setup packet

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPESEL

Pipe Window Select Register
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPESEL : Pipe Window Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No pipe selected

0x1 : 0x1

Pipe 1

0x2 : 0x2

Pipe 2

0x3 : 0x3

Pipe 3

0x4 : 0x4

Pipe 4

0x5 : 0x5

Pipe 5

0x6 : 0x6

Pipe 6

0x7 : 0x7

Pipe 7

0x8 : 0x8

Pipe 8

0x9 : 0x9

Pipe 9

: Others

Setting prohibited

End of enumeration elements list.

PIPECFG

Pipe Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPNUM : Endpoint Number
bits : 0 - 2 (3 bit)
access : read-write

DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Receiving direction

#1 : 1

Transmitting direction

End of enumeration elements list.

SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Continue pipe operation after transfer ends

#1 : 1

Disable pipe after transfer ends

End of enumeration elements list.

CNTMD : Continuous Transfer Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Discontinuous transfer mode

#1 : 1

Continuous transfer mode

End of enumeration elements list.

DBLB : Double Buffer Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Single buffer

#1 : 1

Double buffer

End of enumeration elements list.

BFRE : BRDY Interrupt Operation Specification
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Generate BRDY interrupt on transmitting or receiving data

#1 : 1

Generate BRDY interrupt on completion of reading data

End of enumeration elements list.

TYPE : Transfer Type
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : 00

Pipe not used

#01 : 01

(Pipe 1 to 5) Bulk transfer (Pipe 6 to 9) Setting prohibited

#10 : 10

(Pipe 1 to 5) Setting prohibited (Pipe 6 to 9) Interrupt transfer

#11 : 11

(Pipe 1 to 2) Isochronous transfer (Pipe 3 to 9) Setting prohibited

End of enumeration elements list.

PIPEBUF

Pipe Buffer Register
address_offset : 0x6A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFNMB : Buffer Number
bits : 0 - 6 (7 bit)
access : read-write

BUFSIZE : Buffer Size
bits : 10 - 13 (4 bit)
access : read-write

PIPEMAXP

Pipe Maximum Packet Size Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPS : Maximum Packet Size
bits : 0 - 9 (10 bit)
access : read-write

DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write

PIPEPERI

Pipe Cycle Control Register
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IITV : Interval Error Detection Interval
bits : 0 - 1 (2 bit)
access : read-write

IFIS : Isochronous IN Buffer Flush
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not flush buffer

#1 : 1

Flush buffer

End of enumeration elements list.

PIPE1CTR

Pipe %s Control Register
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPE2CTR

Pipe %s Control Register
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPE3CTR

Pipe %s Control Register
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPE4CTR

Pipe %s Control Register
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

DVSTCTR0

Device State Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RHST : USB Bus Reset Status Flag
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

#000 : 000

Communication speed indeterminate (powered state or no connection)

#001 : 001

Host controller mode Low-speed connection Device controller mode USB bus reset in progress or low-speed connection

#010 : 010

Host controller mode Full-speed connection Device controller mode USB bus reset in progress or full-speed connection

#011 : 011

Host controller mode High-speed connection Device controller mode USB bus reset in progress or high-speed connection

#1xx : 1xx

Host controller mode USB bus reset in progress Device controller mode Setting prohibited

End of enumeration elements list.

UACT : USB Bus Operation Enable for the Host Controller Operation
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable downstream port (disable SOF or micro-SOF transmission)

#1 : 1

Enable downstream port (enable SOF or micro-SOF transmission)

End of enumeration elements list.

RESUME : Resume Signal Output for the Host Controller Operation
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not output resume signal

#1 : 1

Output resume signal

End of enumeration elements list.

USBRST : USB Bus Reset Output for the Host Controller Operation
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not output USB bus reset signal

#1 : 1

Output USB bus reset signal

End of enumeration elements list.

RWUPE : Remote Wakeup Detection Enable for the Host Controller Operation
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable downstream port remote wakeup

#1 : 1

Enable downstream port remote wakeup

End of enumeration elements list.

WKUP : Remote Wakeup Output for the Device Controller Operation
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not output remote wakeup signal

#1 : 1

Output remote wakeup signal

End of enumeration elements list.

VBUSEN : USBHS_VBUSEN Output Pin Control
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output low on external USBHS_VBUSEN pin

#1 : 1

Output high on external USBHS_VBUSEN pin

End of enumeration elements list.

EXICEN : USBHS_EXICEN Output Pin Control
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output low on external USBHS_EXICEN pin

#1 : 1

Output high on external USBHS_EXICEN pin

End of enumeration elements list.

HNPBTOA : Host Negotiation Protocol (HNP) Control
bits : 11 - 10 (0 bit)
access : read-write

PIPE5CTR

Pipe %s Control Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPE6CTR

Pipe %s Control Register
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPE7CTR

Pipe %s Control Register
address_offset : 0x88 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPE8CTR

Pipe %s Control Register
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPE9CTR

Pipe %s Control Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depends on buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Set the expected value for the next transaction to DATA1. This bit is read as 0.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear the expected value for the next transaction to DATA0

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable (initialize all buffers)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto response mode

#1 : 1

Enable auto response mode

End of enumeration elements list.

CSSTS : CSSTS Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start-split (SSPLIT) transaction, or processing for devices that are not using split transactions, in progress.

#1 : 1

Complete-split (CSPLIT) transaction in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear CSSTS to 0

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access disabled

#1 : 1

Buffer access enabled

End of enumeration elements list.

PIPE1TRE

Pipe %s Transaction Counter Enable Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear current counter value

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable transaction counter

#1 : 1

Enable transaction counter

End of enumeration elements list.

PIPE1TRN

Pipe %s Transaction Counter Register
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write

PIPE2TRE

Pipe %s Transaction Counter Enable Register
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear current counter value

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable transaction counter

#1 : 1

Enable transaction counter

End of enumeration elements list.

PIPE2TRN

Pipe %s Transaction Counter Register
address_offset : 0x96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write

PIPE3TRE

Pipe %s Transaction Counter Enable Register
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear current counter value

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable transaction counter

#1 : 1

Enable transaction counter

End of enumeration elements list.

PIPE3TRN

Pipe %s Transaction Counter Register
address_offset : 0x9A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write

PIPE4TRE

Pipe %s Transaction Counter Enable Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear current counter value

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable transaction counter

#1 : 1

Enable transaction counter

End of enumeration elements list.

PIPE4TRN

Pipe %s Transaction Counter Register
address_offset : 0x9E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write

PIPE5TRE

Pipe %s Transaction Counter Enable Register
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid (writing 0 has no effect)

#1 : 1

Clear current counter value

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable transaction counter

#1 : 1

Enable transaction counter

End of enumeration elements list.

PIPE5TRN

Pipe %s Transaction Counter Register
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write

TESTMODE

USB Test Mode Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UTST : Test Mode
bits : 0 - 2 (3 bit)
access : read-write

DEVADD0

Device Address %s Configuration Register
address_offset : 0xD0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD1

Device Address %s Configuration Register
address_offset : 0xD2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD2

Device Address %s Configuration Register
address_offset : 0xD4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD3

Device Address %s Configuration Register
address_offset : 0xD6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD4

Device Address %s Configuration Register
address_offset : 0xD8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD5

Device Address %s Configuration Register
address_offset : 0xDA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD6

Device Address %s Configuration Register
address_offset : 0xDC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD7

Device Address %s Configuration Register
address_offset : 0xDE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD8

Device Address %s Configuration Register
address_offset : 0xE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADD9

Device Address %s Configuration Register
address_offset : 0xE2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

DEVADDA

Device Address A Configuration Register
address_offset : 0xE4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Do not use DEVADDm

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

High speed

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Connect directly to the USBHS port

: Others

Port number of the hub

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Connect directly to the USBHS port

: Others

USB address of the hub. The value as 0xB or more is reserved.

End of enumeration elements list.

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ChipSelect

USBHS

Peripheral Memory Blocks

Registers

SYSCFG

LPCTRL

LPSTS

CFIFO

CFIFOL

CFIFOLL

BCCTRL

PL1CTRL1

PL1CTRL2

HL1CTRL1

HL1CTRL2

CFIFOH

DPUSR0R

DPUSR1R

DPUSR2R

DPUSRCR

CFIFOHH

D0FIFO

D1FIFO

D0FIFOL

D1FIFOL

D0FIFOLL

D1FIFOLL

D0FIFOH

D1FIFOH

D0FIFOHH

D1FIFOHH

BUSWAIT

CFIFOSEL

CFIFOCTR

D0FIFOSEL

D0FIFOCTR

D1FIFOSEL

D1FIFOCTR

INTENB0

INTENB1

BRDYENB

NRDYENB

BEMPENB

SOFCFG

PHYSET

SYSSTS0

INTSTS0

INTSTS1

BRDYSTS

NRDYSTS

BEMPSTS

FRMNUM

UFRMNUM

USBADDR

USBREQ

USBVAL

USBINDX

USBLENG

DCPCFG

DCPMAXP

PLLSTA

DCPCTR

PIPESEL

PIPECFG

PIPEBUF

PIPEMAXP

PIPEPERI

PIPE1CTR

PIPE2CTR

PIPE3CTR

PIPE4CTR

DVSTCTR0

PIPE5CTR

PIPE6CTR

PIPE7CTR

PIPE8CTR

PIPE9CTR

PIPE1TRE

PIPE1TRN

PIPE2TRE