Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
ECC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECEMF : ECC Error Message Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
There is not bit error in present RAM output data.
#1 : 1
There is bit error in present RAM output data.
End of enumeration elements list.
ECER1F : ECC Error Detection and Correction Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
After clearing this bit, 1-bit error correction has not occurred.
#1 : 1
1-bit error has occurred.
End of enumeration elements list.
ECER2F : 2-bit ECC Error Detection Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
After clearing this bit, 2-bit error has not occurred.
#1 : 1
2-bit error has occurred.
End of enumeration elements list.
EC1EDIC : ECC 1-bit error Detection Interrupt Control
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable 1-bit error detection interrupt request.
#1 : 1
Enable 1-bit error detection interrupt request.
End of enumeration elements list.
EC2EDIC : ECC 2-bit error Detection Interrupt Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable 2-bit error detection interrupt request.
#1 : 1
Enable 2-bit error detection interrupt request.
End of enumeration elements list.
EC1ECP : ECC 1-bit error Correction Permission
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
At 1-bit error detection, the error correction is executed.
#1 : 1
At 1-bit error detection, the error correction is not executed.
End of enumeration elements list.
ECERVF : ECC Error Judgment Enable Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Error judgment disable.
#1 : 1
Error judgment enable.
End of enumeration elements list.
ECER1C : Accumulating ECC Error Detection and Correction Flag Clear
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear accumulating ECC error detection and correction flag.
End of enumeration elements list.
ECER2C : 2-bit ECC Error Detection Flag Clear
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear 2-bit ECC error detection flag.
End of enumeration elements list.
ECOVFF : ECC Overflow Detection Flag
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear ECC overflow detection flag.
End of enumeration elements list.
EMCA : Access Control to ECC Mode Select bit
bits : 14 - 14 (1 bit)
access : read-write
ECSEDF0 : ECC Single bit Error Address Detection Flag
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
#0 : 0
There is not bit error in EC710EAD0 after reset or clearing ECER1F bit.
#1 : 1
Address captured in EC710EAD0 shows that 1-bit error occurred and captured.
End of enumeration elements list.
ECDEDF0 : ECC Dual bit Error Address Detection Flag
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
#0 : 0
There is not bit error in EC710EAD0 after reset or clearing ECER2F bit.
#1 : 1
Address captured in EC710EAD0 shows that 2-bit error occurred and captured.
End of enumeration elements list.
ECC Error Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECEAD : ECC Error Address
bits : 0 - 9 (10 bit)
access : read-only
ECC Test Mode Control Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECDCS : ECC Decode Input Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Input lower 32 bits of RAM output data to data area of decode circuit.
#1 : 1
Input ECEDB31-0 in EC710TED register to data area of decode circuit.
End of enumeration elements list.
ECTMCE : ECC Test Mode Control Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The access to test mode register and bit is disabled.
#1 : 1
The access to test mode register and bit is enabled.
End of enumeration elements list.
ETMA : ECC test mode bit access control
bits : 14 - 14 (1 bit)
access : read-write
ECC Test Substitute Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECEDB : ECC Test Substitute Data
bits : 0 - 30 (31 bit)
access : read-write
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