\n
address_offset : 0x0 Bytes (0x0)
size : 0x7 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x101C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10C0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
D/A Data Register %s
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADR : D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.
bits : 0 - 14 (15 bit)
access : read-write
D/A Amplifier Stabilization Wait Control Register
address_offset : 0x101C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAASW0 : D/A Amplifier Stabilization Wait 0
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Amplifier stabilization wait off (output) for channel 0
#1 : 1
Amplifier stabilization wait on (high-Z) for channel 0.
End of enumeration elements list.
DAASW1 : D/A Amplifier Stabilization Wait 1
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Amplifier stabilization wait off (output) for channel 1
#1 : 1
Amplifier stabilization wait on (high-Z) for channel 1.
End of enumeration elements list.
D/A A/D Synchronous Unit Select Register
address_offset : 0x10C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMADSEL1 : A/D Unit 1 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Unit 1 is not selected.
#1 : 1
Unit 1 is selected.
End of enumeration elements list.
D/A Data Register %s
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADR : D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.
bits : 0 - 14 (15 bit)
access : read-write
D/A Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAE : D/A Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
D/A conversion is independently controlled on channels 0 and 1.
#1 : 1
D/A conversion on channels 0 and 1 is controlled as a single whole.
End of enumeration elements list.
DAOE0 : D/A Output Enable 0
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Analog output of channel 0 (DA0) is disabled.
#1 : 1
D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled.
End of enumeration elements list.
DAOE1 : D/A Output Enable 1
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Analog output of channel 1 (DA1) is disabled.
#1 : 1
D/A conversion of channel 1 is enabled. Analog output of channel 1 (DA1) is enabled.
End of enumeration elements list.
DADRm Format Select Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPSEL : DADRm Format Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Right justified format.
#1 : 1
Left justified format.
End of enumeration elements list.
D/A-A/D Synchronous Start Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAADST : D/A-A/D Synchronous Conversion
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled).
#1 : 1
D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled).
End of enumeration elements list.
D/A Output Amplifier Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAAMP0 : Amplifier Control 0
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output amplifier of channel 0 is not used.
#1 : 1
Output amplifier of channel 0 is used.
End of enumeration elements list.
DAAMP1 : Amplifier Control 1
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output amplifier of channel 1 is not used.
#1 : 1
Output amplifier of channel 1 is used.
End of enumeration elements list.
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