Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REN : Receive Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the receive operation.
#1 : 1
Enables the receive operation.
End of enumeration elements list.
TEN : Transmit Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the transmit operation.
#1 : 1
Enables the transmit operation.
End of enumeration elements list.
MUEN : Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
This module is not muted.
#1 : 1
This module is muted.
End of enumeration elements list.
CKDV : Serial Oversampling Clock Division Ratio
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
CLK
0x1 : 0x1
CLK/2
0x2 : 0x2
CLK/4
0x3 : 0x3
CLK/8
0x4 : 0x4
CLK/16
0x5 : 0x5
CLK/32
0x6 : 0x6
CLK/64
0x7 : 0x7
CLK/128
0x8 : 0x8
CLK/6
0x9 : 0x9
CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)
0xA : 0xA
CLK/24
0xB : 0xB
CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)
0xC : 0xC
CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)
: others
Settings other than above are prohibited.
End of enumeration elements list.
DEL : Serial Data Delay
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
1 clock cycle delay between SSIWS and SSIDATA
#1 : 1
No delay between SSIWS and SSIDATA
End of enumeration elements list.
PDTA : Parallel Data Alignment
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits)
#1 : 1
The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits)
End of enumeration elements list.
SDTA : Serial Data Alignment
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmitting and receiving in the order of serial data and padding bits
#1 : 1
Transmitting and receiving in the order of padding bits and serial data
End of enumeration elements list.
SPDP : Serial Padding Polarity
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Padding bits are low.
#1 : 1
Padding bits are high.
End of enumeration elements list.
SWSP : Serial WS Polarity
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
SSIWS is low for 1st channel, high for 2nd channel.
#1 : 1
SSIWS is high for 1st channel, low for 2nd channel.
End of enumeration elements list.
SCKP : Serial Bit Clock Polarity
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge).
#1 : 1
SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge).
End of enumeration elements list.
SWSD : Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited.
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Serial word select is input, slave mode.
#1 : 1
Serial word select is output, master mode.
End of enumeration elements list.
SWL : System Word LengthSet the system word length to the bit clock frequency/2 fs.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bits (serial bit clock frequency = 16fs )
#001 : 001
16 bits (serial bit clock frequency = 32fs )
#010 : 010
24 bits (serial bit clock frequency = 48fs )
#011 : 011
32 bits (serial bit clock frequency = 64fs )
: others
Settings other than above are prohibited.
End of enumeration elements list.
DWL : Data Word Length
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bits
#001 : 001
16 bits
#010 : 010
18 bits
#011 : 011
20 bits
#100 : 100
22 bits
#101 : 101
24 bits
: others
Settings other than above are prohibited.
End of enumeration elements list.
CHNL : Channels
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#00 : 00
One channel
: others
Settings other than above are prohibited.
End of enumeration elements list.
IIEN : Idle Mode Interrupt Enable
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables an idle mode interrupt.
#1 : 1
Enables an idle mode interrupt.
End of enumeration elements list.
ROIEN : Receive Overflow Interrupt Enable
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables an overflow interrupt.
#1 : 1
Enables an overflow interrupt.
End of enumeration elements list.
RUIEN : Receive Underflow Interrupt Enable
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables an underflow interrupt.
#1 : 1
Enables an underflow interrupt.
End of enumeration elements list.
TOIEN : Transmit Overflow Interrupt Enable
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables an overflow interrupt.
#1 : 1
Enables an overflow interrupt.
End of enumeration elements list.
TUIEN : Transmit Underflow Interrupt Enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables an underflow interrupt.
#1 : 1
Enables an underflow interrupt.
End of enumeration elements list.
CKS : Oversampling Clock Select
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
AUDIO_CLK input
#1 : 1
Setting prohibited
End of enumeration elements list.
FIFO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFRST : Receive FIFO Data Register Reset
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clears the receive data FIFO reset.
#1 : 1
Initiates the receive data FIFO reset.
End of enumeration elements list.
TFRST : Transmit FIFO Data Register Reset
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clears the transmit data FIFO reset.
#1 : 1
Initiates the transmit data FIFO reset.
End of enumeration elements list.
RIE : Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive data full interrupt (RXI) request is disabled
#1 : 1
Receive data full interrupt (RXI) request is enabled
End of enumeration elements list.
TIE : Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data empty interrupt (TXI) request is disabled
#1 : 1
Transmit data empty interrupt (TXI) request is enabled
End of enumeration elements list.
RTRG : Receive Data Trigger Number
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
1
#01 : 01
2
#10 : 10
4
#11 : 11
6
End of enumeration elements list.
TTRG : Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
7 (1)
#01 : 01
6 (2)
#10 : 10
4 (4)
#11 : 11
2 (6)
End of enumeration elements list.
SSIRST : SSI soft ware reset
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clears the SSI software reset.
#1 : 1
initiates the SSI software reset.
End of enumeration elements list.
AUCKE : Oversampling Clock Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
The oversampling clock is disabled.
#1 : 1
The oversampling clock is enabled.
End of enumeration elements list.
FIFO Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDF : Receive Data Full Flag NOTE: Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC[3:0] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Number of received data bytes in SSIFRDR is less than the set receive trigger number.
#1 : 1
Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number.
End of enumeration elements list.
RDC : Receive Data Indicate Flag(Indicates the number of data units stored in SSIFRDR)
bits : 8 - 10 (3 bit)
access : read-only
TDE : Transmit Data Empty Flag NOTE: Since the SSIFTDR register is a 32-byte FIFO register, the maximum number of bytes that can be written to it while the TDE flag is 1 is 8 - TDC[3:0]. If writing data to the SSIFTDR register is continued after all the data is written, writing will be invalid and an overflow occurs.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number.
#1 : 1
Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number.
End of enumeration elements list.
TDC : Transmit Data Indicate Flag(Indicates the number of data units stored in SSIFTDR)
bits : 24 - 26 (3 bit)
access : read-only
Transmit FIFO Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SSIFTDR : SSIFTDR is a write-only FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. NOTE: that when the SSIFTDR register is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs.
bits : 0 - 30 (31 bit)
access : write-only
Receive FIFO Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SSIFRDR : SSIFRDR is a read-only FIFO register consisting of eight stages of 32-bit registers for storing serially received data.
bits : 0 - 30 (31 bit)
access : read-only
Audio Format Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OMOD : Audio Format Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
I2S format
#01 : 01
TDM format
#10 : 10
Monaural format
#11 : 11
Setting prohibited.
End of enumeration elements list.
LRCONT : Whether to Enable LRCK/FS Continuation
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables LRCK/FS continuation.
#1 : 1
Enables LRCK/FS continuation.
End of enumeration elements list.
BCKASTP : Whether to Enable Stopping BCK Output When SSIE is in Idle Status
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Always outputs BCK to the SSIBCK pin.
#1 : 1
Automatically controls output of BCK to the SSIBCK pin.
End of enumeration elements list.
Status Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDFS : RDF Setting Condition Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
SSIFRDR has one stage or more data size
#00001 : 00001
SSIFRDR has two stages or more data size (snip)
#11110 : 11110
SSIFRDR has thirty-one stages or more data size
#11111 : 11111
SSIFRDR has thirty-two stages or more data size.
End of enumeration elements list.
TDES : TDE Setting Condition Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
SSIFTDR has one stage or more free space
#00001 : 00001
SSIFTDR has two stages or more free space (snip)
#11110 : 11110
SSIFTDR has thirty-one stages or more free space
#11111 : 11111
SSIFTDR has thirty-two stages or more free space.
End of enumeration elements list.
Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDST : Idle Mode Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Serial bus is operating.
#1 : 1
The current communication is stopped.
End of enumeration elements list.
RSWNO : Receive Serial Word Number
bits : 1 - 0 (0 bit)
access : read-only
RCHNO : Receive Channel Number.These bits are read as 00b.
bits : 2 - 2 (1 bit)
access : read-only
TSWNO : Transmit Serial Word Number
bits : 4 - 3 (0 bit)
access : read-only
TCHNO : Transmit Channel Number
bits : 5 - 5 (1 bit)
access : read-only
IIRQ : Idle Mode Interrupt Status Flag
bits : 25 - 24 (0 bit)
access : read-only
Enumeration:
#0 : 0
This module is not in idle state.
#1 : 1
This module is in idle state.
End of enumeration elements list.
ROIRQ : Receive Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
No receive overflow has occurred.
#1 : 1
A receive overflow has occurred.
End of enumeration elements list.
RUIRQ : Receive Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
No receive underflow has occurred.
#1 : 1
A receive underflow has occurred.
End of enumeration elements list.
TOIRQ : Transmit Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
No transmit overflow has occurred.
#1 : 1
A transmit overflow has occurred.
End of enumeration elements list.
TUIRQ : Transmit Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
No transmit underflow has occurred.
#1 : 1
A transmit underflow has occurred.
End of enumeration elements list.
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