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WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x2 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

Registers

WDTRR

WDTCR

WDTSR

WDTRCR

WDTCSTPR


WDTRR

WDT Refresh Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTRR WDTRR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WDTRR

WDTRR : WDTRR is an 8-bit register that refreshes the down-counter of the WDT.
bits : 0 - 6 (7 bit)
access : read-write


WDTCR

WDT Control Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCR WDTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOPS CKS RPES RPSS

TOPS : Timeout Period Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

1,024 cycles (03FFh)

#01 : 01

4,096 cycles (0FFFh)

#10 : 10

8,192 cycles (1FFFh)

#11 : 11

16,384 cycles (3FFFh)

End of enumeration elements list.

CKS : Clock Division Ratio Selection
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#0001 : 0001

PCLK/4

#0100 : 0100

PCLK/64

#1111 : 1111

PCLK/128

#0110 : 0110

PCLK/512

#0111 : 0111

PCLK/2048

#1000 : 1000

PCLK/8192

: others

setting prohibited

End of enumeration elements list.

RPES : Window End Position Selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : 00

75 percent

#01 : 01

50 percent

#10 : 10

25 percent

#11 : 11

0 percent (window end position is not specified)

End of enumeration elements list.

RPSS : Window Start Position Selection
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : 00

25 percent

#01 : 01

50 percent

#10 : 10

75 percent

#11 : 11

100 percent (window start position is not specified)

End of enumeration elements list.


WDTSR

WDT Status Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTSR WDTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTVAL UNDFF REFEF

CNTVAL : Down-Counter ValueValue counted by the down-counter
bits : 0 - 12 (13 bit)
access : read-only

UNDFF : Underflow Flag
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

No underflow occurred

#1 : 1

Underflow occurred

End of enumeration elements list.

REFEF : Refresh Error Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

No refresh error occurred

#1 : 1

Refresh error occurred

End of enumeration elements list.


WDTRCR

WDT Reset Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTRCR WDTRCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RSTIRQS

RSTIRQS : Reset Interrupt Request Selection
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt request or interrupt request output is enabled

#1 : 1

Reset output is enabled.

End of enumeration elements list.


WDTCSTPR

WDT Count Stop Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCSTPR WDTCSTPR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLCSTP

SLCSTP : Sleep-Mode Count Stop Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Count stop is disabled.

#1 : 1

Count is stopped at a transition to sleep mode.

End of enumeration elements list.



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