Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
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System Configuration Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBE : USB Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
USB operation is disabled.
#1 : 1
USB operation is enabled.
End of enumeration elements list.
DPRPU : D+ Line Resistor Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulling up the line is disabled.
#1 : 1
Pulling up the line is enabled.
End of enumeration elements list.
DRPD : D+/D- Line Resistor Control
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulling down the lines is disabled.
#1 : 1
Pulling down the lines is enabled.
End of enumeration elements list.
DCFM : Controller Function Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Function controller is selected.
#1 : 1
Host controller is selected.
End of enumeration elements list.
SCKE : USB Clock Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stops supplying the clock signal to the USB.
#1 : 1
Enables supplying the clock signal to the USB.
End of enumeration elements list.
CFIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write
CFIFO Port Register L
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0
D0FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write
D0FIFO Port Register L
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0
D1FIFO Port Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write
D1FIFO Port Register L
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D1FIFO
reset_Mask : 0x0
CFIFO Port Select Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : CFIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
DCP (Default control pipe)
#0001 : 0001
Pipe 1
#0010 : 0010
Pipe 2
#0011 : 0011
Pipe 3
#0100 : 0100
Pipe 4
#0101 : 0101
Pipe 5
#0110 : 0110
Pipe 6
#0111 : 0111
Pipe 7
#1000 : 1000
Pipe 8
#1001 : 1001
Pipe 9
: others
Setting prohibited
End of enumeration elements list.
ISEL : CFIFO Port Access Direction When DCP is Selected
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reading from the buffer memory is selected
#1 : 1
Writing to the buffer memory is selected
End of enumeration elements list.
BIGEND : CFIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
MBW : CFIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
The buffer pointer is not rewound.
#1 : 1
The buffer pointer is rewound.
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.)
#1 : 1
The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO.
End of enumeration elements list.
CFIFO Port Control Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 7 (8 bit)
access : read-only
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access is disabled.
#1 : 1
FIFO port access is enabled.
End of enumeration elements list.
BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Clears the buffer memory on the CPU side
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Writing ended
End of enumeration elements list.
D0FIFO Port Select Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
DCP (Default control pipe)
#0001 : 0001
Pipe 1
#0010 : 0010
Pipe 2
#0011 : 0011
Pipe 3
#0100 : 0100
Pipe 4
#0101 : 0101
Pipe 5
#0110 : 0110
Pipe 6
#0111 : 0111
Pipe 7
#1000 : 1000
Pipe 8
#1001 : 1001
Pipe 9
: others
Setting prohibited
End of enumeration elements list.
BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
MBW : FIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA/DTC transfer request is disabled.
#1 : 1
DMA/DTC transfer request is enabled.
End of enumeration elements list.
DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled.
End of enumeration elements list.
REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
The buffer pointer is not rewound.
#1 : 1
The buffer pointer is rewound.
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)
#1 : 1
The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)
End of enumeration elements list.
D0FIFO Port Control Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 7 (8 bit)
access : read-only
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access is disabled.
#1 : 1
FIFO port access is enabled.
End of enumeration elements list.
BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Clears the buffer memory on the CPU side
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Writing ended
End of enumeration elements list.
D1FIFO Port Select Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
DCP (Default control pipe)
#0001 : 0001
Pipe 1
#0010 : 0010
Pipe 2
#0011 : 0011
Pipe 3
#0100 : 0100
Pipe 4
#0101 : 0101
Pipe 5
#0110 : 0110
Pipe 6
#0111 : 0111
Pipe 7
#1000 : 1000
Pipe 8
#1001 : 1001
Pipe 9
: others
Setting prohibited
End of enumeration elements list.
BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
MBW : FIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA/DTC transfer request is disabled.
#1 : 1
DMA/DTC transfer request is enabled.
End of enumeration elements list.
DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled.
End of enumeration elements list.
REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
The buffer pointer is not rewound.
#1 : 1
The buffer pointer is rewound.
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)
#1 : 1
The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)
End of enumeration elements list.
D1FIFO Port Control Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 7 (8 bit)
access : read-only
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access is disabled.
#1 : 1
FIFO port access is enabled.
End of enumeration elements list.
BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Clears the buffer memory on the CPU side
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Writing ended
End of enumeration elements list.
Interrupt Enable Register 0
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRDYE : Buffer Ready Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
NRDYE : Buffer Not Ready Response Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
BEMPE : Buffer Empty Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
CTRE : Control Transfer Stage Transition Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
DVSE : Device State Transition Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
SOFE : Frame Number Update Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
RSME : Resume Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
VBSE : VBUS Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
Interrupt Enable Register 1
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACKE : Setup Transaction Normal Response Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
SIGNE : Setup Transaction Error Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
EOFERRE : EOF Error Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
ATTCHE : Connection Detection Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
DTCHE : Disconnection Detection Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
BCHGE : USB Bus Change Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
OVRCRE : Overcurrent Input Change Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
BRDY Interrupt Enable Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BRDYE : BRDY Interrupt Enable for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE1BRDYE : BRDY Interrupt Enable for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE2BRDYE : BRDY Interrupt Enable for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE3BRDYE : BRDY Interrupt Enable for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE4BRDYE : BRDY Interrupt Enable for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE5BRDYE : BRDY Interrupt Enable for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE6BRDYE : BRDY Interrupt Enable for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE7BRDYE : BRDY Interrupt Enable for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE8BRDYE : BRDY Interrupt Enable for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE9BRDYE : BRDY Interrupt Enable for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
NRDY Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0NRDYE : NRDY Interrupt Enable for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE1NRDYE : NRDY Interrupt Enable for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE2NRDYE : NRDY Interrupt Enable for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE3NRDYE : NRDY Interrupt Enable for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE4NRDYE : NRDY Interrupt Enable for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE5NRDYE : NRDY Interrupt Enable for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE6NRDYE : NRDY Interrupt Enable for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE7NRDYE : NRDY Interrupt Enable for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE8NRDYE : NRDY Interrupt Enable for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE9NRDYE : NRDY Interrupt Enable for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
BEMP Interrupt Enable Register
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BEMPE : BEMP Interrupt Enable for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE1BEMPE : BEMP Interrupt Enable for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE2BEMPE : BEMP Interrupt Enable for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE3BEMPE : BEMP Interrupt Enable for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE4BEMPE : BEMP Interrupt Enable for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE5BEMPE : BEMP Interrupt Enable for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE6BEMPE : BEMP Interrupt Enable for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE7BEMPE : BEMP Interrupt Enable for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE8BEMPE : BEMP Interrupt Enable for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE9BEMPE : BEMP Interrupt Enable for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
SOF Output Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGESTS : Edge Interrupt Output Status Monitor
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
before stopping the clock supply to the USB module
#1 : 1
the edge interrupt output signal is in the middle of the edge processing
End of enumeration elements list.
BRDYM : BRDY Interrupt Status Clear Timing
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software clears the status.
#1 : 1
The USB clears the status when data has been read from the FIFO buffer or data has been written to the FIFO buffer.
End of enumeration elements list.
TRNENSEL : Transaction-Enabled Time Select
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
For non-low-speed communication
#1 : 1
For low-speed communication
End of enumeration elements list.
System Configuration Status Register 0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LNST : USB Data Line Status Monitor
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#00 : 00
SE0
#01 : 01
J-State
#10 : 10
K-State
#11 : 11
SE1
End of enumeration elements list.
IDMON : External ID0 Input Pin Monitor
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
USB0_ID pin is low
#1 : 1
USB0_ID pin is high
End of enumeration elements list.
SOFEA : Active Monitor When the Host Controller is Selected.
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
SOF output is stopped.
#1 : 1
SOF output is operating.
End of enumeration elements list.
HTACT : USB Host Sequencer Status Monitor
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Host sequencer of the USB is completely stopped.
#1 : 1
Host sequencer of the USB is not completely stopped.
End of enumeration elements list.
OVCMON : External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin.
bits : 14 - 14 (1 bit)
access : read-only
Interrupt Status Register 0
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTSQ : Control Transfer Stage
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#000 : 000
Idle or setup stage
#001 : 001
Control read data stage
#010 : 010
Control read status stage
#011 : 011
Control write data stage
#100 : 100
Control write status stage
#101 : 101
Control write (no data) status stage
#110 : 110
Control transfer sequence error
: others
Setting prohibited
End of enumeration elements list.
VALID : USB Request Reception
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Setup packet is not received
#1 : 1
Setup packet is received
End of enumeration elements list.
DVSQ : Device State
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#000 : 000
Powered state
#001 : 001
Default state
#010 : 010
Address state
#011 : 011
Configured state
: others
Suspended state
End of enumeration elements list.
VBSTS : VBUS Input Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
USB0_VBUS pin is low.
#1 : 1
USB0_VBUS pin is high.
End of enumeration elements list.
BRDY : Buffer Ready Interrupt Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
BRDY interrupts are not generated.
#1 : 1
BRDY interrupts are generated.
End of enumeration elements list.
NRDY : Buffer Not Ready Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
NRDY interrupts are not generated.
#1 : 1
NRDY interrupts are generated.
End of enumeration elements list.
BEMP : Buffer Empty Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
BEMP interrupts are not generated.
#1 : 1
BEMP interrupts are generated.
End of enumeration elements list.
CTRT : Control Transfer Stage Transition Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Control transfer stage transition interrupts are not generated.
#1 : 1
Control transfer stage transition interrupts are generated.
End of enumeration elements list.
DVST : Device State Transition Interrupt Status
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Device state transition interrupts are not generated.
#1 : 1
Device state transition interrupts are generated.
End of enumeration elements list.
SOFR : Frame Number Refresh Interrupt Status
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
SOF interrupts are not generated.
#1 : 1
SOF interrupts are generated.
End of enumeration elements list.
RESM : Resume Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Resume interrupts are not generated.
#1 : 1
Resume interrupts are generated.
End of enumeration elements list.
VBINT : VBUS Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
VBUS interrupts are not generated.
#1 : 1
VBUS interrupts are generated.
End of enumeration elements list.
Deep Software Standby USB Transceiver Control/Pin Monitor Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRPC0 : USB Single End Receiver Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Input through the DP and DM inputs is disabled.
#1 : 1
Input through the DP and DM inputs is enabled.
End of enumeration elements list.
RPUE0 : DP Pull-Up Resistor Control
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables DP pull-up resistor.
#1 : 1
Enables DP pull-up resistor.
End of enumeration elements list.
DRPD0 : D+/D- Pull-Down Resistor Control
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables DP/DM pull-down resistor.
#1 : 1
Enables DP/DM pull-down resistor.
End of enumeration elements list.
FIXPHY0 : USB Transceiver Output Fix
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
The outputs are fixed in normal mode and on return from deep software standby mode.
#1 : 1
The outputs are fixed on transitions to deep software standby mode.
End of enumeration elements list.
DP0 : USB0 D+ InputIndicates the D+ input signal of the USB.
bits : 16 - 15 (0 bit)
access : read-only
DM0 : USB D-InputIndicates the D- input signal of the USB.
bits : 17 - 16 (0 bit)
access : read-only
DOVCA0 : USB OVRCURA InputIndicates the OVRCURA input signal of the USB.
bits : 20 - 19 (0 bit)
access : read-only
DOVCB0 : USB OVRCURB InputIndicates the OVRCURB input signal of the USB.
bits : 21 - 20 (0 bit)
access : read-only
DVBSTS0 : USB VBUS InputIndicates the VBUS input signal of the USB.
bits : 23 - 22 (0 bit)
access : read-only
Deep Software Standby USB Suspend/Resume Interrupt Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPINTE0 : USB DP Interrupt Enable/Clear
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery from deep software standby mode is disabled.
#1 : 1
Recovery from deep software standby mode is enabled.
End of enumeration elements list.
DMINTE0 : USB DM Interrupt Enable/Clear
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery from deep software standby mode is disabled.
#1 : 1
Recovery from deep software standby mode is enabled.
End of enumeration elements list.
DOVRCRAE0 : USB OVRCURA Interrupt Enable/Clear
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery from deep software standby mode is disabled.
#1 : 1
Recovery from deep software standby mode is enabled.
End of enumeration elements list.
DOVRCRBE0 : USB OVRCURB Interrupt Enable/Clear
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery from deep software standby mode is disabled.
#1 : 1
Recovery from deep software standby mode is enabled.
End of enumeration elements list.
DVBSE0 : USB VBUS Interrupt Enable/Clear
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery from deep software standby mode is disabled.
#1 : 1
Recovery from deep software standby mode is enabled.
End of enumeration elements list.
DPINT0 : USB DP Interrupt Source Recovery
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
#0 : 0
The system has not returned from deep software standby mode.
#1 : 1
The system has returned from deep software standby mode.
End of enumeration elements list.
DMINT0 : USB DM Interrupt Source Recovery
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
#0 : 0
The system has not returned from deep software standby mode.
#1 : 1
The system has returned from deep software standby mode.
End of enumeration elements list.
DOVRCRA0 : USB OVRCURA Interrupt Source Recovery
bits : 20 - 19 (0 bit)
access : read-only
Enumeration:
#0 : 0
The system has not returned from deep software standby mode.
#1 : 1
The system has returned from deep software standby mode.
End of enumeration elements list.
DOVRCRB0 : USB OVRCURB Interrupt Source Recovery
bits : 21 - 20 (0 bit)
access : read-only
Enumeration:
#0 : 0
The system has not returned from deep software standby mode.
#1 : 1
The system has returned from deep software standby mode.
End of enumeration elements list.
DVBINT0 : USB VBUS Interrupt Source Recovery
bits : 23 - 22 (0 bit)
access : read-only
Enumeration:
#0 : 0
The system has not returned from deep software standby mode.
#1 : 1
The system has returned from deep software standby mode.
End of enumeration elements list.
Interrupt Status Register 1
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACK : Setup Transaction Normal Response Interrupt Status
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
SACK interrupts are not generated.
#1 : 1
SACK interrupts are generated.
End of enumeration elements list.
SIGN : Setup Transaction Error Interrupt Status
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
SIGN interrupts are not generated.
#1 : 1
SIGN interrupts are generated.
End of enumeration elements list.
EOFERR : EOF Error Detection Interrupt Status
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
EOFERR interrupts are not generated.
#1 : 1
EOFERR interrupts are generated.
End of enumeration elements list.
ATTCH : ATTCH Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
ATTCH interrupts are not generated.
#1 : 1
ATTCH interrupts are generated.
End of enumeration elements list.
DTCH : USB Disconnection Detection Interrupt Status
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTCH interrupts are not generated.
#1 : 1
DTCH interrupts are generated.
End of enumeration elements list.
BCHG : USB Bus Change Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
BCHG interrupts are not generated.
#1 : 1
BCHG interrupts are generated.
End of enumeration elements list.
OVRCR : Overcurrent Input Change Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
OVRCR interrupts are not generated.
#1 : 1
OVRCR interrupts are generated.
End of enumeration elements list.
BRDY Interrupt Status Register
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BRDY : BRDY Interrupt Status for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE1BRDY : BRDY Interrupt Status for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE2BRDY : BRDY Interrupt Status for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE3BRDY : BRDY Interrupt Status for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE4BRDY : BRDY Interrupt Status for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE5BRDY : BRDY Interrupt Status for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE6BRDY : BRDY Interrupt Status for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE7BRDY : BRDY Interrupt Status for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE8BRDY : BRDY Interrupt Status for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE9BRDY : BRDY Interrupt Status for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
NRDY Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0NRDY : NRDY Interrupt Status for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE1NRDY : NRDY Interrupt Status for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE2NRDY : NRDY Interrupt Status for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE3NRDY : NRDY Interrupt Status for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE4NRDY : NRDY Interrupt Status for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE5NRDY : NRDY Interrupt Status for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE6NRDY : NRDY Interrupt Status for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE7NRDY : NRDY Interrupt Status for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE8NRDY : NRDY Interrupt Status for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE9NRDY : NRDY Interrupt Status for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
BEMP Interrupt Status Register
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BEMP : BEMP Interrupt Status for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE1BEMP : BEMP Interrupt Status for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE2BEMP : BEMP Interrupt Status for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE3BEMP : BEMP Interrupt Status for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE4BEMP : BEMP Interrupt Status for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE5BEMP : BEMP Interrupt Status for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE6BEMP : BEMP Interrupt Status for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE7BEMP : BEMP Interrupt Status for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE8BEMP : BEMP Interrupt Status for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE9BEMP : BEMP Interrupt Status for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
Frame Number Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRNM : Frame NumberLatest frame number
bits : 0 - 9 (10 bit)
access : read-only
CRCE : Receive Data Error
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
No error
#1 : 1
An error occurred
End of enumeration elements list.
OVRN : Overrun/Underrun Detection Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
No error
#1 : 1
An error occurred
End of enumeration elements list.
Device State Change Register
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVCHG : Device State Change
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the writing to the USBADDR.STSRECOV[3:0] bits and USBADDR.USBADDR[6:0].
#1 : 1
Enables the writing to the USBADDR.STSRECOV[3:0] bits and USBADDR.USBADDR[6:0].
End of enumeration elements list.
USB Address Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBADDR : USB AddressWhen the function controller is selected, these bits indicate the USB address assigned by the host when the SET_ADDRESS request is successfully processed.
bits : 0 - 5 (6 bit)
access : read-write
STSRECOV : Status Recovery
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#0100 : 0100
Return to the low-speed state (bits DVSTCTR0.RHST[2:0] = 001b (Recovery when the host controller is selected))
#1000 : 1000
Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b (Recovery when the host controller is selected))
#1001 : 1001
Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state) (Recovery when the function controller is selected)
#1010 : 1010
Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state) (Recovery when the function controller is selected)
#1011 : 1011
Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state) (Recovery when the function controller is selected)
: others
Settings other than above are prohibited.
End of enumeration elements list.
USB Request Type Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BMREQUESTTYPE : Request TypeThese bits store the USB request bmRequestType value.
bits : 0 - 6 (7 bit)
access : read-write
BREQUEST : RequestThese bits store the USB request bRequest value.
bits : 8 - 14 (7 bit)
access : read-write
USB Request Value Register
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WVALUE : ValueThese bits store the USB request wValue value.
bits : 0 - 14 (15 bit)
access : read-write
USB Request Index Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINDEX : IndexThese bits store the USB request wIndex value.
bits : 0 - 14 (15 bit)
access : read-write
USB Request Length Register
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLENGTUH : LengthThese bits store the USB request wLength value.
bits : 0 - 14 (15 bit)
access : read-write
DCP Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data receiving direction
#1 : 1
Data transmitting direction
End of enumeration elements list.
SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pipe continued at the end of transfer
#1 : 1
Pipe disabled at the end of transfer
End of enumeration elements list.
DCP Maximum Packet Size Register
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPS : Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP.
bits : 0 - 5 (6 bit)
access : read-write
DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Address 0000
#0001 : 0001
Address 0001
#0010 : 0010
Address 0010
#0011 : 0011
Address 0011
#0100 : 0100
Address 0100
#0101 : 0101
Address 0101
: others
Settings prohibited.
End of enumeration elements list.
DCP Control Register
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
CCPL : Control Transfer End Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Completion of control transfer is enabled.
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
DCP is not used for the transaction.
#1 : 1
DCP is used for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Monitor
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
SUREQCLR : SUREQ Bit Clear
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Clears the SUREQ bit to 0.
End of enumeration elements list.
SUREQ : Setup Token Transmission
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Transmits the setup packet.
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
Pipe Window Select Register
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPESEL : Pipe Window Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
No pipe selected
#0001 : 0001
PIPE1
#0010 : 0010
PIPE2
#0011 : 0011
PIPE3
#0100 : 0100
PIPE4
#0101 : 0101
PIPE5
#0110 : 0110
PIPE6
#0111 : 0111
PIPE7
#1000 : 1000
PIPE8
#1001 : 1001
PIPE9
: others
Settings prohibited.
End of enumeration elements list.
Pipe Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPNUM : Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe.
bits : 0 - 2 (3 bit)
access : read-write
DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receiving direction
#1 : 1
Transmitting direction
End of enumeration elements list.
SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pipe assignment continued at the end of transfer
#1 : 1
Pipe assignment disabled at the end of transfer
End of enumeration elements list.
DBLB : Double Buffer Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single buffer
#1 : 1
Double buffer
End of enumeration elements list.
BFRE : BRDY Interrupt Operation Specification
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
BRDY interrupt upon transmitting or receiving data
#1 : 1
BRDY interrupt upon completion of reading data
End of enumeration elements list.
TYPE : Transfer Type
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Pipe not used
#01 : 01
Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9)
#10 : 10
Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9)
#11 : 11
Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9)
End of enumeration elements list.
Pipe Maximum Packet Size Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPS : Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.)
bits : 0 - 7 (8 bit)
access : read-write
DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Address 0000
#0001 : 0001
Address 0001
#0010 : 0010
Address 0010
#0011 : 0011
Address 0011
#0100 : 0100
Address 0100
#0101 : 0101
Address 0101
: others
Settings prohibited.
End of enumeration elements list.
Pipe Cycle Control Register
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IITV : Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2.
bits : 0 - 1 (2 bit)
access : read-write
IFIS : Isochronous IN Buffer Flush
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
The buffer is not flushed.
#1 : 1
The buffer is flushed.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used for the transaction.
#1 : 1
The relevant pipe is used for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response is disabled.
#1 : 1
Auto response is enabled.
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x72 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used for the transaction.
#1 : 1
The relevant pipe is used for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response is disabled.
#1 : 1
Auto response is enabled.
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used for the transaction.
#1 : 1
The relevant pipe is used for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response is disabled.
#1 : 1
Auto response is enabled.
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x76 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used for the transaction.
#1 : 1
The relevant pipe is used for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response is disabled.
#1 : 1
Auto response is enabled.
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used for the transaction.
#1 : 1
The relevant pipe is used for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response is disabled.
#1 : 1
Auto response is enabled.
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x7A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used at the USB bus.
#1 : 1
The relevant pipe is used at the USB bus.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled (all buffers are initialized)
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used at the USB bus.
#1 : 1
The relevant pipe is used at the USB bus.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled (all buffers are initialized)
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x7E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used at the USB bus.
#1 : 1
The relevant pipe is used at the USB bus.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled (all buffers are initialized)
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
Device State Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RHST : USB Bus Reset Status
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#000 : 000
Communication speed not determined
#001 : 001
Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected)
#010 : 010
Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected)
#011 : 011
Setting prohibited
: others
USB bus reset in progress(When the host controller function is selected)
End of enumeration elements list.
UACT : USB Bus Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Downstream port is disabled (SOF transmission is disabled).
#1 : 1
Downstream port is enabled (SOF transmission is enabled).
End of enumeration elements list.
RESUME : Resume Output
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Resume signal is not output.
#1 : 1
Resume signal is output.
End of enumeration elements list.
USBRST : USB Bus Reset Output
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
USB bus reset signal is not output.
#1 : 1
USB bus reset signal is output.
End of enumeration elements list.
RWUPE : Wakeup Detection Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Downstream port wakeup is disabled.
#1 : 1
Downstream port wakeup is enabled.
End of enumeration elements list.
WKUP : Wakeup Output
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Remote wakeup signal is not output.
#1 : 1
Remote wakeup signal is output.
End of enumeration elements list.
VBUSEN : USB0_VBUSEN Output Pin Control
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
External USB0_VBUSEN pin outputs low
#1 : 1
External USB0_VBUSEN pin outputs high
End of enumeration elements list.
EXICEN : USB0_EXICEN Output Pin Control
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
External USB0_EXICEN pin outputs low
#1 : 1
External USB0_EXICEN pin outputs high
End of enumeration elements list.
HNPBTOA : Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Switching from device B to device A is enabled
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The relevant pipe is not used at the USB bus.
#1 : 1
The relevant pipe is used at the USB bus.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled (all buffers are initialized)
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
Pipe %s Transaction Counter Enable Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Pipe %s Transaction Counter Register
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
Pipe %s Transaction Counter Enable Register
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Pipe %s Transaction Counter Register
address_offset : 0x96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
Pipe %s Transaction Counter Enable Register
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Pipe %s Transaction Counter Register
address_offset : 0x9A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
Pipe %s Transaction Counter Enable Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Pipe %s Transaction Counter Register
address_offset : 0x9E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
Pipe %s Transaction Counter Enable Register
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Pipe %s Transaction Counter Register
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
Device Address %s Configuration Register
address_offset : 0xD0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xD2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xD4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xD6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xD8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xDA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
PHY Cross Point Adjustment Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEWR00 : Receiver Cross Point Adjustment 00
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reserved
#1 : 1
Host or device controller mode.
End of enumeration elements list.
SLEWR01 : Receiver Cross Point Adjustment 01
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reserved
#1 : 1
Host or device controller mode.
End of enumeration elements list.
SLEWF00 : Receiver Cross Point Adjustment 00
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reserved
#1 : 1
Host or device controller mode.
End of enumeration elements list.
SLEWF01 : Receiver Cross Point Adjustment 01
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reserved
#1 : 1
Host or device controller mode.
End of enumeration elements list.
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