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CAN0

Peripheral Memory Blocks

address_offset : 0x200 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x204 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x206 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x207 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x208 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x209 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20A Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20B Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20C Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20D Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20E Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x400 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x42C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x820 Bytes (0x0)
size : 0x39 byte (0x0)
mem_usage : registers
protection :

Registers

MB0_ID

MB0_DL

MB0_D0

MB0_D1

MB0_D2

MB0_D3

MB0_D4

MB0_D5

MB0_D6

MB0_D7

MB0_TS

MB1_ID

MB1_DL

MB1_D0

MB1_D1

MB1_D2

MB1_D3

MB1_D4

MB1_D5

MB1_D6

MB1_D7

MB1_TS

MB2_ID

MB2_DL

MB2_D0

MB2_D1

MB2_D2

MB2_D3

MB2_D4

MB2_D5

MB2_D6

MB2_D7

MB2_TS

MB3_ID

MB3_DL

MB3_D0

MB3_D1

MB3_D2

MB3_D3

MB3_D4

MB3_D5

MB3_D6

MB3_D7

MB3_TS

MB4_ID

MB4_DL

MB4_D0

MB4_D1

MB4_D2

MB4_D3

MB4_D4

MB4_D5

MB4_D6

MB4_D7

MB4_TS

MB5_ID

MB5_DL

MB5_D0

MB5_D1

MB5_D2

MB5_D3

MB5_D4

MB5_D5

MB5_D6

MB5_D7

MB5_TS

MB6_ID

MB6_DL

MB6_D0

MB6_D1

MB6_D2

MB6_D3

MB6_D4

MB6_D5

MB6_D6

MB6_D7

MB6_TS

MB7_ID

MB7_DL

MB7_D0

MB7_D1

MB7_D2

MB7_D3

MB7_D4

MB7_D5

MB7_D6

MB7_D7

MB7_TS

MB8_ID

MB8_DL

MB8_D0

MB8_D1

MB8_D2

MB8_D3

MB8_D4

MB8_D5

MB8_D6

MB8_D7

MB8_TS

MB9_ID

MB9_DL

MB9_D0

MB9_D1

MB9_D2

MB9_D3

MB9_D4

MB9_D5

MB9_D6

MB9_D7

MB9_TS

MB10_ID

MB10_DL

MB10_D0

MB10_D1

MB10_D2

MB10_D3

MB10_D4

MB10_D5

MB10_D6

MB10_D7

MB10_TS

MB11_ID

MB11_DL

MB11_D0

MB11_D1

MB11_D2

MB11_D3

MB11_D4

MB11_D5

MB11_D6

MB11_D7

MB11_TS

MB12_ID

MB12_DL

MB12_D0

MB12_D1

MB12_D2

MB12_D3

MB12_D4

MB12_D5

MB12_D6

MB12_D7

MB12_TS

MB13_ID

MB13_DL

MB13_D0

MB13_D1

MB13_D2

MB13_D3

MB13_D4

MB13_D5

MB13_D6

MB13_D7

MB13_TS

MB14_ID

MB14_DL

MB14_D0

MB14_D1

MB14_D2

MB14_D3

MB14_D4

MB14_D5

MB14_D6

MB14_D7

MB14_TS

MB15_ID

MB15_DL

MB15_D0

MB15_D1

MB15_D2

MB15_D3

MB15_D4

MB15_D5

MB15_D6

MB15_D7

MB15_TS

MB16_ID

MB16_DL

MB16_D0

MB16_D1

MB16_D2

MB16_D3

MB16_D4

MB16_D5

MB16_D6

MB16_D7

MB16_TS

MB17_ID

MB17_DL

MB17_D0

MB17_D1

MB17_D2

MB17_D3

MB17_D4

MB17_D5

MB17_D6

MB17_D7

MB17_TS

MB18_ID

MB18_DL

MB18_D0

MB18_D1

MB18_D2

MB18_D3

MB18_D4

MB18_D5

MB18_D6

MB18_D7

MB18_TS

MB19_ID

MB19_DL

MB19_D0

MB19_D1

MB19_D2

MB19_D3

MB19_D4

MB19_D5

MB19_D6

MB19_D7

MB19_TS

MB20_ID

MB20_DL

MB20_D0

MB20_D1

MB20_D2

MB20_D3

MB20_D4

MB20_D5

MB20_D6

MB20_D7

MB20_TS

MB21_ID

MB21_DL

MB21_D0

MB21_D1

MB21_D2

MB21_D3

MB21_D4

MB21_D5

MB21_D6

MB21_D7

MB21_TS

MB22_ID

MB22_DL

MB22_D0

MB22_D1

MB22_D2

MB22_D3

MB22_D4

MB22_D5

MB22_D6

MB22_D7

MB22_TS

MB23_ID

MB23_DL

MB23_D0

MB23_D1

MB23_D2

MB23_D3

MB23_D4

MB23_D5

MB23_D6

MB23_D7

MB23_TS

MB24_ID

MB24_DL

MB24_D0

MB24_D1

MB24_D2

MB24_D3

MB24_D4

MB24_D5

MB24_D6

MB24_D7

MB24_TS

MB25_ID

MB25_DL

MB25_D0

MB25_D1

MB25_D2

MB25_D3

MB25_D4

MB25_D5

MB25_D6

MB25_D7

MB25_TS

MB26_ID

MB26_DL

MB26_D0

MB26_D1

MB26_D2

MB26_D3

MB26_D4

MB26_D5

MB26_D6

MB26_D7

MB26_TS

MB27_ID

MB27_DL

MB27_D0

MB27_D1

MB27_D2

MB27_D3

MB27_D4

MB27_D5

MB27_D6

MB27_D7

MB27_TS

MB28_ID

MB28_DL

MB28_D0

MB28_D1

MB28_D2

MB28_D3

MB28_D4

MB28_D5

MB28_D6

MB28_D7

MB28_TS

MB29_ID

MB29_DL

MB29_D0

MB29_D1

MB29_D2

MB29_D3

MB29_D4

MB29_D5

MB29_D6

MB29_D7

MB29_TS

MB30_ID

MB30_DL

MB30_D0

MB30_D1

MB30_D2

MB30_D3

MB30_D4

MB30_D5

MB30_D6

MB30_D7

MB30_TS

MB31_ID

MB31_DL

MB31_D0

MB31_D1

MB31_D2

MB31_D3

MB31_D4

MB31_D5

MB31_D6

MB31_D7

MB31_TS

MKR0

MKR1

MKR2

MKR3

MKR4

MKR5

MKR6

MKR7

FIDCR0

FIDCR1

MKIVLR

MIER

MIER_FIFO

MCTL_TX0

MCTL_RX0

MCTL_TX1

MCTL_RX1

MCTL_TX2

MCTL_RX2

MCTL_TX3

MCTL_RX3

MCTL_TX4

MCTL_RX4

MCTL_TX5

MCTL_RX5

MCTL_TX6

MCTL_RX6

MCTL_TX7

MCTL_RX7

MCTL_TX8

MCTL_RX8

MCTL_TX9

MCTL_RX9

MCTL_TX10

MCTL_RX10

MCTL_TX11

MCTL_RX11

MCTL_TX12

MCTL_RX12

MCTL_TX13

MCTL_RX13

MCTL_TX14

MCTL_RX14

MCTL_TX15

MCTL_RX15

MCTL_TX16

MCTL_RX16

MCTL_TX17

MCTL_RX17

MCTL_TX18

MCTL_RX18

MCTL_TX19

MCTL_RX19

MCTL_TX20

MCTL_RX20

MCTL_TX21

MCTL_RX21

MCTL_TX22

MCTL_RX22

MCTL_TX23

MCTL_RX23

MCTL_TX24

MCTL_RX24

MCTL_TX25

MCTL_RX25

MCTL_TX26

MCTL_RX26

MCTL_TX27

MCTL_RX27

MCTL_TX28

MCTL_RX28

MCTL_TX29

MCTL_RX29

MCTL_TX30

MCTL_RX30

MCTL_TX31

MCTL_RX31

CTLR

STR

BCR

RFCR

RFPCR

TFCR

TFPCR

EIER

EIFR

RECR

TECR

ECSR

CSSR

MSSR

MSMR

TSR

AFSR

TCR


MB0_ID

Mailbox Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_ID MB0_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB0_DL

Mailbox Register
address_offset : 0x204 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_DL MB0_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB0_D0

Mailbox Register
address_offset : 0x206 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_D0 MB0_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB0_D1

Mailbox Register
address_offset : 0x207 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_D1 MB0_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB0_D2

Mailbox Register
address_offset : 0x208 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_D2 MB0_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB0_D3

Mailbox Register
address_offset : 0x209 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_D3 MB0_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB0_D4

Mailbox Register
address_offset : 0x20A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_D4 MB0_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB0_D5

Mailbox Register
address_offset : 0x20B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_D5 MB0_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB0_D6

Mailbox Register
address_offset : 0x20C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_D6 MB0_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB0_D7

Mailbox Register
address_offset : 0x20D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_D7 MB0_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB0_TS

Mailbox Register
address_offset : 0x20E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB0_TS MB0_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB1_ID

Mailbox Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_ID MB1_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB1_DL

Mailbox Register
address_offset : 0x214 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_DL MB1_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB1_D0

Mailbox Register
address_offset : 0x216 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_D0 MB1_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB1_D1

Mailbox Register
address_offset : 0x217 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_D1 MB1_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB1_D2

Mailbox Register
address_offset : 0x218 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_D2 MB1_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB1_D3

Mailbox Register
address_offset : 0x219 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_D3 MB1_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB1_D4

Mailbox Register
address_offset : 0x21A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_D4 MB1_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB1_D5

Mailbox Register
address_offset : 0x21B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_D5 MB1_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB1_D6

Mailbox Register
address_offset : 0x21C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_D6 MB1_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB1_D7

Mailbox Register
address_offset : 0x21D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_D7 MB1_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB1_TS

Mailbox Register
address_offset : 0x21E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB1_TS MB1_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB2_ID

Mailbox Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_ID MB2_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB2_DL

Mailbox Register
address_offset : 0x224 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_DL MB2_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB2_D0

Mailbox Register
address_offset : 0x226 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_D0 MB2_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB2_D1

Mailbox Register
address_offset : 0x227 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_D1 MB2_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB2_D2

Mailbox Register
address_offset : 0x228 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_D2 MB2_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB2_D3

Mailbox Register
address_offset : 0x229 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_D3 MB2_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB2_D4

Mailbox Register
address_offset : 0x22A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_D4 MB2_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB2_D5

Mailbox Register
address_offset : 0x22B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_D5 MB2_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB2_D6

Mailbox Register
address_offset : 0x22C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_D6 MB2_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB2_D7

Mailbox Register
address_offset : 0x22D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_D7 MB2_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB2_TS

Mailbox Register
address_offset : 0x22E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB2_TS MB2_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB3_ID

Mailbox Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_ID MB3_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB3_DL

Mailbox Register
address_offset : 0x234 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_DL MB3_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB3_D0

Mailbox Register
address_offset : 0x236 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_D0 MB3_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB3_D1

Mailbox Register
address_offset : 0x237 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_D1 MB3_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB3_D2

Mailbox Register
address_offset : 0x238 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_D2 MB3_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB3_D3

Mailbox Register
address_offset : 0x239 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_D3 MB3_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB3_D4

Mailbox Register
address_offset : 0x23A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_D4 MB3_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB3_D5

Mailbox Register
address_offset : 0x23B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_D5 MB3_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB3_D6

Mailbox Register
address_offset : 0x23C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_D6 MB3_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB3_D7

Mailbox Register
address_offset : 0x23D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_D7 MB3_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB3_TS

Mailbox Register
address_offset : 0x23E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB3_TS MB3_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB4_ID

Mailbox Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_ID MB4_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB4_DL

Mailbox Register
address_offset : 0x244 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_DL MB4_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB4_D0

Mailbox Register
address_offset : 0x246 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_D0 MB4_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB4_D1

Mailbox Register
address_offset : 0x247 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_D1 MB4_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB4_D2

Mailbox Register
address_offset : 0x248 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_D2 MB4_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB4_D3

Mailbox Register
address_offset : 0x249 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_D3 MB4_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB4_D4

Mailbox Register
address_offset : 0x24A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_D4 MB4_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB4_D5

Mailbox Register
address_offset : 0x24B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_D5 MB4_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB4_D6

Mailbox Register
address_offset : 0x24C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_D6 MB4_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB4_D7

Mailbox Register
address_offset : 0x24D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_D7 MB4_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB4_TS

Mailbox Register
address_offset : 0x24E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB4_TS MB4_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB5_ID

Mailbox Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_ID MB5_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB5_DL

Mailbox Register
address_offset : 0x254 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_DL MB5_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB5_D0

Mailbox Register
address_offset : 0x256 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_D0 MB5_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB5_D1

Mailbox Register
address_offset : 0x257 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_D1 MB5_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB5_D2

Mailbox Register
address_offset : 0x258 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_D2 MB5_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB5_D3

Mailbox Register
address_offset : 0x259 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_D3 MB5_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB5_D4

Mailbox Register
address_offset : 0x25A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_D4 MB5_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB5_D5

Mailbox Register
address_offset : 0x25B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_D5 MB5_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB5_D6

Mailbox Register
address_offset : 0x25C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_D6 MB5_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB5_D7

Mailbox Register
address_offset : 0x25D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_D7 MB5_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB5_TS

Mailbox Register
address_offset : 0x25E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB5_TS MB5_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB6_ID

Mailbox Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_ID MB6_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB6_DL

Mailbox Register
address_offset : 0x264 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_DL MB6_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB6_D0

Mailbox Register
address_offset : 0x266 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_D0 MB6_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB6_D1

Mailbox Register
address_offset : 0x267 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_D1 MB6_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB6_D2

Mailbox Register
address_offset : 0x268 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_D2 MB6_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB6_D3

Mailbox Register
address_offset : 0x269 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_D3 MB6_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB6_D4

Mailbox Register
address_offset : 0x26A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_D4 MB6_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB6_D5

Mailbox Register
address_offset : 0x26B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_D5 MB6_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB6_D6

Mailbox Register
address_offset : 0x26C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_D6 MB6_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB6_D7

Mailbox Register
address_offset : 0x26D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_D7 MB6_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB6_TS

Mailbox Register
address_offset : 0x26E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB6_TS MB6_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB7_ID

Mailbox Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_ID MB7_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB7_DL

Mailbox Register
address_offset : 0x274 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_DL MB7_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB7_D0

Mailbox Register
address_offset : 0x276 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_D0 MB7_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB7_D1

Mailbox Register
address_offset : 0x277 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_D1 MB7_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB7_D2

Mailbox Register
address_offset : 0x278 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_D2 MB7_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB7_D3

Mailbox Register
address_offset : 0x279 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_D3 MB7_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB7_D4

Mailbox Register
address_offset : 0x27A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_D4 MB7_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB7_D5

Mailbox Register
address_offset : 0x27B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_D5 MB7_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB7_D6

Mailbox Register
address_offset : 0x27C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_D6 MB7_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB7_D7

Mailbox Register
address_offset : 0x27D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_D7 MB7_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB7_TS

Mailbox Register
address_offset : 0x27E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB7_TS MB7_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB8_ID

Mailbox Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_ID MB8_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB8_DL

Mailbox Register
address_offset : 0x284 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_DL MB8_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB8_D0

Mailbox Register
address_offset : 0x286 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_D0 MB8_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB8_D1

Mailbox Register
address_offset : 0x287 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_D1 MB8_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB8_D2

Mailbox Register
address_offset : 0x288 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_D2 MB8_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB8_D3

Mailbox Register
address_offset : 0x289 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_D3 MB8_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB8_D4

Mailbox Register
address_offset : 0x28A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_D4 MB8_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB8_D5

Mailbox Register
address_offset : 0x28B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_D5 MB8_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB8_D6

Mailbox Register
address_offset : 0x28C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_D6 MB8_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB8_D7

Mailbox Register
address_offset : 0x28D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_D7 MB8_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB8_TS

Mailbox Register
address_offset : 0x28E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB8_TS MB8_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB9_ID

Mailbox Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_ID MB9_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB9_DL

Mailbox Register
address_offset : 0x294 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_DL MB9_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB9_D0

Mailbox Register
address_offset : 0x296 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_D0 MB9_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB9_D1

Mailbox Register
address_offset : 0x297 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_D1 MB9_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB9_D2

Mailbox Register
address_offset : 0x298 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_D2 MB9_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB9_D3

Mailbox Register
address_offset : 0x299 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_D3 MB9_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB9_D4

Mailbox Register
address_offset : 0x29A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_D4 MB9_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB9_D5

Mailbox Register
address_offset : 0x29B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_D5 MB9_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB9_D6

Mailbox Register
address_offset : 0x29C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_D6 MB9_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB9_D7

Mailbox Register
address_offset : 0x29D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_D7 MB9_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB9_TS

Mailbox Register
address_offset : 0x29E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB9_TS MB9_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB10_ID

Mailbox Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_ID MB10_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB10_DL

Mailbox Register
address_offset : 0x2A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_DL MB10_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB10_D0

Mailbox Register
address_offset : 0x2A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_D0 MB10_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB10_D1

Mailbox Register
address_offset : 0x2A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_D1 MB10_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB10_D2

Mailbox Register
address_offset : 0x2A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_D2 MB10_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB10_D3

Mailbox Register
address_offset : 0x2A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_D3 MB10_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB10_D4

Mailbox Register
address_offset : 0x2AA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_D4 MB10_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB10_D5

Mailbox Register
address_offset : 0x2AB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_D5 MB10_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB10_D6

Mailbox Register
address_offset : 0x2AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_D6 MB10_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB10_D7

Mailbox Register
address_offset : 0x2AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_D7 MB10_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB10_TS

Mailbox Register
address_offset : 0x2AE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB10_TS MB10_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB11_ID

Mailbox Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_ID MB11_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB11_DL

Mailbox Register
address_offset : 0x2B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_DL MB11_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB11_D0

Mailbox Register
address_offset : 0x2B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_D0 MB11_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB11_D1

Mailbox Register
address_offset : 0x2B7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_D1 MB11_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB11_D2

Mailbox Register
address_offset : 0x2B8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_D2 MB11_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB11_D3

Mailbox Register
address_offset : 0x2B9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_D3 MB11_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB11_D4

Mailbox Register
address_offset : 0x2BA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_D4 MB11_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB11_D5

Mailbox Register
address_offset : 0x2BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_D5 MB11_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB11_D6

Mailbox Register
address_offset : 0x2BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_D6 MB11_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB11_D7

Mailbox Register
address_offset : 0x2BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_D7 MB11_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB11_TS

Mailbox Register
address_offset : 0x2BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB11_TS MB11_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB12_ID

Mailbox Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_ID MB12_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB12_DL

Mailbox Register
address_offset : 0x2C4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_DL MB12_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB12_D0

Mailbox Register
address_offset : 0x2C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_D0 MB12_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB12_D1

Mailbox Register
address_offset : 0x2C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_D1 MB12_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB12_D2

Mailbox Register
address_offset : 0x2C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_D2 MB12_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB12_D3

Mailbox Register
address_offset : 0x2C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_D3 MB12_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB12_D4

Mailbox Register
address_offset : 0x2CA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_D4 MB12_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB12_D5

Mailbox Register
address_offset : 0x2CB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_D5 MB12_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB12_D6

Mailbox Register
address_offset : 0x2CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_D6 MB12_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB12_D7

Mailbox Register
address_offset : 0x2CD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_D7 MB12_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB12_TS

Mailbox Register
address_offset : 0x2CE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB12_TS MB12_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB13_ID

Mailbox Register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_ID MB13_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB13_DL

Mailbox Register
address_offset : 0x2D4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_DL MB13_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB13_D0

Mailbox Register
address_offset : 0x2D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_D0 MB13_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB13_D1

Mailbox Register
address_offset : 0x2D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_D1 MB13_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB13_D2

Mailbox Register
address_offset : 0x2D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_D2 MB13_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB13_D3

Mailbox Register
address_offset : 0x2D9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_D3 MB13_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB13_D4

Mailbox Register
address_offset : 0x2DA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_D4 MB13_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB13_D5

Mailbox Register
address_offset : 0x2DB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_D5 MB13_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB13_D6

Mailbox Register
address_offset : 0x2DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_D6 MB13_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB13_D7

Mailbox Register
address_offset : 0x2DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_D7 MB13_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB13_TS

Mailbox Register
address_offset : 0x2DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB13_TS MB13_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB14_ID

Mailbox Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_ID MB14_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB14_DL

Mailbox Register
address_offset : 0x2E4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_DL MB14_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB14_D0

Mailbox Register
address_offset : 0x2E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_D0 MB14_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB14_D1

Mailbox Register
address_offset : 0x2E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_D1 MB14_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB14_D2

Mailbox Register
address_offset : 0x2E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_D2 MB14_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB14_D3

Mailbox Register
address_offset : 0x2E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_D3 MB14_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB14_D4

Mailbox Register
address_offset : 0x2EA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_D4 MB14_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB14_D5

Mailbox Register
address_offset : 0x2EB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_D5 MB14_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB14_D6

Mailbox Register
address_offset : 0x2EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_D6 MB14_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB14_D7

Mailbox Register
address_offset : 0x2ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_D7 MB14_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB14_TS

Mailbox Register
address_offset : 0x2EE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB14_TS MB14_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB15_ID

Mailbox Register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_ID MB15_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB15_DL

Mailbox Register
address_offset : 0x2F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_DL MB15_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB15_D0

Mailbox Register
address_offset : 0x2F6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_D0 MB15_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB15_D1

Mailbox Register
address_offset : 0x2F7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_D1 MB15_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB15_D2

Mailbox Register
address_offset : 0x2F8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_D2 MB15_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB15_D3

Mailbox Register
address_offset : 0x2F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_D3 MB15_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB15_D4

Mailbox Register
address_offset : 0x2FA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_D4 MB15_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB15_D5

Mailbox Register
address_offset : 0x2FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_D5 MB15_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB15_D6

Mailbox Register
address_offset : 0x2FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_D6 MB15_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB15_D7

Mailbox Register
address_offset : 0x2FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_D7 MB15_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB15_TS

Mailbox Register
address_offset : 0x2FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB15_TS MB15_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB16_ID

Mailbox Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_ID MB16_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB16_DL

Mailbox Register
address_offset : 0x304 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_DL MB16_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB16_D0

Mailbox Register
address_offset : 0x306 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_D0 MB16_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB16_D1

Mailbox Register
address_offset : 0x307 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_D1 MB16_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB16_D2

Mailbox Register
address_offset : 0x308 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_D2 MB16_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB16_D3

Mailbox Register
address_offset : 0x309 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_D3 MB16_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB16_D4

Mailbox Register
address_offset : 0x30A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_D4 MB16_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB16_D5

Mailbox Register
address_offset : 0x30B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_D5 MB16_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB16_D6

Mailbox Register
address_offset : 0x30C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_D6 MB16_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB16_D7

Mailbox Register
address_offset : 0x30D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_D7 MB16_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB16_TS

Mailbox Register
address_offset : 0x30E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB16_TS MB16_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB17_ID

Mailbox Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_ID MB17_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB17_DL

Mailbox Register
address_offset : 0x314 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_DL MB17_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB17_D0

Mailbox Register
address_offset : 0x316 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_D0 MB17_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB17_D1

Mailbox Register
address_offset : 0x317 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_D1 MB17_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB17_D2

Mailbox Register
address_offset : 0x318 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_D2 MB17_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB17_D3

Mailbox Register
address_offset : 0x319 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_D3 MB17_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB17_D4

Mailbox Register
address_offset : 0x31A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_D4 MB17_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB17_D5

Mailbox Register
address_offset : 0x31B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_D5 MB17_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB17_D6

Mailbox Register
address_offset : 0x31C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_D6 MB17_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB17_D7

Mailbox Register
address_offset : 0x31D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_D7 MB17_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB17_TS

Mailbox Register
address_offset : 0x31E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB17_TS MB17_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB18_ID

Mailbox Register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_ID MB18_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB18_DL

Mailbox Register
address_offset : 0x324 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_DL MB18_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB18_D0

Mailbox Register
address_offset : 0x326 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_D0 MB18_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB18_D1

Mailbox Register
address_offset : 0x327 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_D1 MB18_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB18_D2

Mailbox Register
address_offset : 0x328 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_D2 MB18_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB18_D3

Mailbox Register
address_offset : 0x329 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_D3 MB18_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB18_D4

Mailbox Register
address_offset : 0x32A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_D4 MB18_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB18_D5

Mailbox Register
address_offset : 0x32B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_D5 MB18_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB18_D6

Mailbox Register
address_offset : 0x32C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_D6 MB18_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB18_D7

Mailbox Register
address_offset : 0x32D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_D7 MB18_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB18_TS

Mailbox Register
address_offset : 0x32E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB18_TS MB18_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB19_ID

Mailbox Register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_ID MB19_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB19_DL

Mailbox Register
address_offset : 0x334 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_DL MB19_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB19_D0

Mailbox Register
address_offset : 0x336 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_D0 MB19_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB19_D1

Mailbox Register
address_offset : 0x337 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_D1 MB19_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB19_D2

Mailbox Register
address_offset : 0x338 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_D2 MB19_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB19_D3

Mailbox Register
address_offset : 0x339 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_D3 MB19_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB19_D4

Mailbox Register
address_offset : 0x33A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_D4 MB19_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB19_D5

Mailbox Register
address_offset : 0x33B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_D5 MB19_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB19_D6

Mailbox Register
address_offset : 0x33C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_D6 MB19_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB19_D7

Mailbox Register
address_offset : 0x33D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_D7 MB19_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB19_TS

Mailbox Register
address_offset : 0x33E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB19_TS MB19_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB20_ID

Mailbox Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_ID MB20_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB20_DL

Mailbox Register
address_offset : 0x344 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_DL MB20_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB20_D0

Mailbox Register
address_offset : 0x346 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_D0 MB20_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB20_D1

Mailbox Register
address_offset : 0x347 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_D1 MB20_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB20_D2

Mailbox Register
address_offset : 0x348 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_D2 MB20_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB20_D3

Mailbox Register
address_offset : 0x349 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_D3 MB20_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB20_D4

Mailbox Register
address_offset : 0x34A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_D4 MB20_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB20_D5

Mailbox Register
address_offset : 0x34B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_D5 MB20_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB20_D6

Mailbox Register
address_offset : 0x34C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_D6 MB20_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB20_D7

Mailbox Register
address_offset : 0x34D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_D7 MB20_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB20_TS

Mailbox Register
address_offset : 0x34E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB20_TS MB20_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB21_ID

Mailbox Register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_ID MB21_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB21_DL

Mailbox Register
address_offset : 0x354 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_DL MB21_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB21_D0

Mailbox Register
address_offset : 0x356 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_D0 MB21_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB21_D1

Mailbox Register
address_offset : 0x357 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_D1 MB21_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB21_D2

Mailbox Register
address_offset : 0x358 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_D2 MB21_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB21_D3

Mailbox Register
address_offset : 0x359 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_D3 MB21_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB21_D4

Mailbox Register
address_offset : 0x35A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_D4 MB21_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB21_D5

Mailbox Register
address_offset : 0x35B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_D5 MB21_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB21_D6

Mailbox Register
address_offset : 0x35C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_D6 MB21_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB21_D7

Mailbox Register
address_offset : 0x35D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_D7 MB21_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB21_TS

Mailbox Register
address_offset : 0x35E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB21_TS MB21_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB22_ID

Mailbox Register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_ID MB22_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB22_DL

Mailbox Register
address_offset : 0x364 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_DL MB22_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB22_D0

Mailbox Register
address_offset : 0x366 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_D0 MB22_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB22_D1

Mailbox Register
address_offset : 0x367 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_D1 MB22_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB22_D2

Mailbox Register
address_offset : 0x368 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_D2 MB22_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB22_D3

Mailbox Register
address_offset : 0x369 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_D3 MB22_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB22_D4

Mailbox Register
address_offset : 0x36A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_D4 MB22_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB22_D5

Mailbox Register
address_offset : 0x36B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_D5 MB22_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB22_D6

Mailbox Register
address_offset : 0x36C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_D6 MB22_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB22_D7

Mailbox Register
address_offset : 0x36D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_D7 MB22_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB22_TS

Mailbox Register
address_offset : 0x36E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB22_TS MB22_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB23_ID

Mailbox Register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_ID MB23_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB23_DL

Mailbox Register
address_offset : 0x374 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_DL MB23_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB23_D0

Mailbox Register
address_offset : 0x376 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_D0 MB23_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB23_D1

Mailbox Register
address_offset : 0x377 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_D1 MB23_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB23_D2

Mailbox Register
address_offset : 0x378 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_D2 MB23_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB23_D3

Mailbox Register
address_offset : 0x379 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_D3 MB23_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB23_D4

Mailbox Register
address_offset : 0x37A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_D4 MB23_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB23_D5

Mailbox Register
address_offset : 0x37B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_D5 MB23_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB23_D6

Mailbox Register
address_offset : 0x37C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_D6 MB23_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB23_D7

Mailbox Register
address_offset : 0x37D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_D7 MB23_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB23_TS

Mailbox Register
address_offset : 0x37E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB23_TS MB23_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB24_ID

Mailbox Register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_ID MB24_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB24_DL

Mailbox Register
address_offset : 0x384 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_DL MB24_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB24_D0

Mailbox Register
address_offset : 0x386 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_D0 MB24_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB24_D1

Mailbox Register
address_offset : 0x387 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_D1 MB24_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB24_D2

Mailbox Register
address_offset : 0x388 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_D2 MB24_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB24_D3

Mailbox Register
address_offset : 0x389 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_D3 MB24_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB24_D4

Mailbox Register
address_offset : 0x38A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_D4 MB24_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB24_D5

Mailbox Register
address_offset : 0x38B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_D5 MB24_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB24_D6

Mailbox Register
address_offset : 0x38C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_D6 MB24_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB24_D7

Mailbox Register
address_offset : 0x38D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_D7 MB24_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB24_TS

Mailbox Register
address_offset : 0x38E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB24_TS MB24_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB25_ID

Mailbox Register
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_ID MB25_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB25_DL

Mailbox Register
address_offset : 0x394 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_DL MB25_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB25_D0

Mailbox Register
address_offset : 0x396 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_D0 MB25_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB25_D1

Mailbox Register
address_offset : 0x397 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_D1 MB25_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB25_D2

Mailbox Register
address_offset : 0x398 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_D2 MB25_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB25_D3

Mailbox Register
address_offset : 0x399 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_D3 MB25_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB25_D4

Mailbox Register
address_offset : 0x39A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_D4 MB25_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB25_D5

Mailbox Register
address_offset : 0x39B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_D5 MB25_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB25_D6

Mailbox Register
address_offset : 0x39C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_D6 MB25_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB25_D7

Mailbox Register
address_offset : 0x39D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_D7 MB25_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB25_TS

Mailbox Register
address_offset : 0x39E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB25_TS MB25_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB26_ID

Mailbox Register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_ID MB26_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB26_DL

Mailbox Register
address_offset : 0x3A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_DL MB26_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB26_D0

Mailbox Register
address_offset : 0x3A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_D0 MB26_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB26_D1

Mailbox Register
address_offset : 0x3A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_D1 MB26_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB26_D2

Mailbox Register
address_offset : 0x3A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_D2 MB26_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB26_D3

Mailbox Register
address_offset : 0x3A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_D3 MB26_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB26_D4

Mailbox Register
address_offset : 0x3AA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_D4 MB26_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB26_D5

Mailbox Register
address_offset : 0x3AB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_D5 MB26_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB26_D6

Mailbox Register
address_offset : 0x3AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_D6 MB26_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB26_D7

Mailbox Register
address_offset : 0x3AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_D7 MB26_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB26_TS

Mailbox Register
address_offset : 0x3AE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB26_TS MB26_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB27_ID

Mailbox Register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_ID MB27_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB27_DL

Mailbox Register
address_offset : 0x3B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_DL MB27_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB27_D0

Mailbox Register
address_offset : 0x3B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_D0 MB27_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB27_D1

Mailbox Register
address_offset : 0x3B7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_D1 MB27_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB27_D2

Mailbox Register
address_offset : 0x3B8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_D2 MB27_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB27_D3

Mailbox Register
address_offset : 0x3B9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_D3 MB27_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB27_D4

Mailbox Register
address_offset : 0x3BA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_D4 MB27_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB27_D5

Mailbox Register
address_offset : 0x3BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_D5 MB27_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB27_D6

Mailbox Register
address_offset : 0x3BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_D6 MB27_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB27_D7

Mailbox Register
address_offset : 0x3BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_D7 MB27_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB27_TS

Mailbox Register
address_offset : 0x3BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB27_TS MB27_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB28_ID

Mailbox Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_ID MB28_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB28_DL

Mailbox Register
address_offset : 0x3C4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_DL MB28_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB28_D0

Mailbox Register
address_offset : 0x3C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_D0 MB28_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB28_D1

Mailbox Register
address_offset : 0x3C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_D1 MB28_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB28_D2

Mailbox Register
address_offset : 0x3C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_D2 MB28_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB28_D3

Mailbox Register
address_offset : 0x3C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_D3 MB28_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB28_D4

Mailbox Register
address_offset : 0x3CA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_D4 MB28_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB28_D5

Mailbox Register
address_offset : 0x3CB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_D5 MB28_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB28_D6

Mailbox Register
address_offset : 0x3CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_D6 MB28_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB28_D7

Mailbox Register
address_offset : 0x3CD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_D7 MB28_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB28_TS

Mailbox Register
address_offset : 0x3CE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB28_TS MB28_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB29_ID

Mailbox Register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_ID MB29_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB29_DL

Mailbox Register
address_offset : 0x3D4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_DL MB29_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB29_D0

Mailbox Register
address_offset : 0x3D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_D0 MB29_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB29_D1

Mailbox Register
address_offset : 0x3D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_D1 MB29_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB29_D2

Mailbox Register
address_offset : 0x3D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_D2 MB29_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB29_D3

Mailbox Register
address_offset : 0x3D9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_D3 MB29_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB29_D4

Mailbox Register
address_offset : 0x3DA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_D4 MB29_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB29_D5

Mailbox Register
address_offset : 0x3DB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_D5 MB29_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB29_D6

Mailbox Register
address_offset : 0x3DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_D6 MB29_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB29_D7

Mailbox Register
address_offset : 0x3DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_D7 MB29_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB29_TS

Mailbox Register
address_offset : 0x3DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB29_TS MB29_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB30_ID

Mailbox Register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_ID MB30_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB30_DL

Mailbox Register
address_offset : 0x3E4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_DL MB30_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB30_D0

Mailbox Register
address_offset : 0x3E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_D0 MB30_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB30_D1

Mailbox Register
address_offset : 0x3E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_D1 MB30_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB30_D2

Mailbox Register
address_offset : 0x3E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_D2 MB30_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB30_D3

Mailbox Register
address_offset : 0x3E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_D3 MB30_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB30_D4

Mailbox Register
address_offset : 0x3EA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_D4 MB30_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB30_D5

Mailbox Register
address_offset : 0x3EB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_D5 MB30_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB30_D6

Mailbox Register
address_offset : 0x3EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_D6 MB30_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB30_D7

Mailbox Register
address_offset : 0x3ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_D7 MB30_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB30_TS

Mailbox Register
address_offset : 0x3EE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB30_TS MB30_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MB31_ID

Mailbox Register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_ID MB31_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MB31_DL

Mailbox Register
address_offset : 0x3F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_DL MB31_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC

DLC : Data Length Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Data length = 0 byte

#0001 : 0001

Data length = 1 byte

#0010 : 0010

Data length = 2 bytes

#0011 : 0011

Data length = 3 bytes

#0100 : 0100

Data length = 4 bytes

#0101 : 0101

Data length = 5 bytes

#0110 : 0110

Data length = 6 bytes

#0111 : 0111

Data length = 7 bytes

: others

Data length = 8 bytes

End of enumeration elements list.


MB31_D0

Mailbox Register
address_offset : 0x3F6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_D0 MB31_D0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA0

DATA0 : Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB31_D1

Mailbox Register
address_offset : 0x3F7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_D1 MB31_D1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA1

DATA1 : Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB31_D2

Mailbox Register
address_offset : 0x3F8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_D2 MB31_D2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA2

DATA2 : Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB31_D3

Mailbox Register
address_offset : 0x3F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_D3 MB31_D3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA3

DATA3 : Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB31_D4

Mailbox Register
address_offset : 0x3FA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_D4 MB31_D4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA4

DATA4 : Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB31_D5

Mailbox Register
address_offset : 0x3FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_D5 MB31_D5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA5

DATA5 : Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB31_D6

Mailbox Register
address_offset : 0x3FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_D6 MB31_D6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA6

DATA6 : Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB31_D7

Mailbox Register
address_offset : 0x3FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_D7 MB31_D7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA7

DATA7 : Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.
bits : 0 - 6 (7 bit)
access : read-write


MB31_TS

Mailbox Register
address_offset : 0x3FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MB31_TS MB31_TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSL TSH

TSL : Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 0 - 6 (7 bit)
access : read-write

TSH : Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
bits : 8 - 14 (7 bit)
access : read-write


MKR0

Mask Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKR0 MKR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write


MKR1

Mask Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKR1 MKR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write


MKR2

Mask Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKR2 MKR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write


MKR3

Mask Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKR3 MKR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write


MKR4

Mask Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKR4 MKR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write


MKR5

Mask Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKR5 MKR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write


MKR6

Mask Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKR6 MKR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write


MKR7

Mask Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKR7 MKR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write


FIDCR0

FIFO Received ID Compare Registers
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIDCR0 FIDCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


FIDCR1

FIFO Received ID Compare Registers
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIDCR1 FIDCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EID SID RTR IDE

EID : Extended ID
bits : 0 - 16 (17 bit)
access : read-write

SID : Standard ID
bits : 18 - 27 (10 bit)
access : read-write

RTR : Remote Transmission Request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data frame

#1 : 1

Remote frame

End of enumeration elements list.

IDE : ID Extension
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard ID

#1 : 1

Extended ID

End of enumeration elements list.


MKIVLR

Mask Invalid Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MKIVLR MKIVLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 MB8 MB9 MB10 MB11 MB12 MB13 MB14 MB15 MB16 MB17 MB18 MB19 MB20 MB21 MB22 MB23 MB24 MB25 MB26 MB27 MB28 MB29 MB30 MB31

MB0 : mailbox 0 Mask Invalid
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB1 : mailbox 1 Mask Invalid
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB2 : mailbox 2 Mask Invalid
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB3 : mailbox 3 Mask Invalid
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB4 : mailbox 4 Mask Invalid
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB5 : mailbox 5 Mask Invalid
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB6 : mailbox 6 Mask Invalid
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB7 : mailbox 7 Mask Invalid
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB8 : mailbox 8 Mask Invalid
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB9 : mailbox 9 Mask Invalid
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB10 : mailbox 10 Mask Invalid
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB11 : mailbox 11 Mask Invalid
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB12 : mailbox 12 Mask Invalid
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB13 : mailbox 13 Mask Invalid
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB14 : mailbox 14 Mask Invalid
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB15 : mailbox 15 Mask Invalid
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB16 : mailbox 16 Mask Invalid
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB17 : mailbox 17 Mask Invalid
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB18 : mailbox 18 Mask Invalid
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB19 : mailbox 19 Mask Invalid
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB20 : mailbox 20 Mask Invalid
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB21 : mailbox 21 Mask Invalid
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB22 : mailbox 22 Mask Invalid
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB23 : mailbox 23 Mask Invalid
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB24 : mailbox 24 Mask Invalid
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB25 : mailbox 25 Mask Invalid
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB26 : mailbox 26 Mask Invalid
bits : 26 - 25 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB27 : mailbox 27 Mask Invalid
bits : 27 - 26 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB28 : mailbox 28 Mask Invalid
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB29 : mailbox 29 Mask Invalid
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB30 : mailbox 30 Mask Invalid
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.

MB31 : mailbox 31 Mask Invalid
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask valid

#1 : 1

Mask invalid

End of enumeration elements list.


MIER

Mailbox Interrupt Enable Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIER MIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 MB8 MB9 MB10 MB11 MB12 MB13 MB14 MB15 MB16 MB17 MB18 MB19 MB20 MB21 MB22 MB23 MB24 MB25 MB26 MB27 MB28 MB29 MB30 MB31

MB0 : mailbox 0 Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB1 : mailbox 1 Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB2 : mailbox 2 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB3 : mailbox 3 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB4 : mailbox 4 Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB5 : mailbox 5 Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB6 : mailbox 6 Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB7 : mailbox 7 Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB8 : mailbox 8 Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB9 : mailbox 9 Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB10 : mailbox 10 Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB11 : mailbox 11 Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB12 : mailbox 12 Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB13 : mailbox 13 Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB14 : mailbox 14 Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB15 : mailbox 15 Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB16 : mailbox 16 Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB17 : mailbox 17 Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB18 : mailbox 18 Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB19 : mailbox 19 Interrupt Enable
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB20 : mailbox 20 Interrupt Enable
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB21 : mailbox 21 Interrupt Enable
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB22 : mailbox 22 Interrupt Enable
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB23 : mailbox 23 Interrupt Enable
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB24 : mailbox 24 Interrupt Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB25 : mailbox 25 Interrupt Enable
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB26 : mailbox 26 Interrupt Enable
bits : 26 - 25 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB27 : mailbox 27 Interrupt Enable
bits : 27 - 26 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB28 : mailbox 28 Interrupt Enable
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB29 : mailbox 29 Interrupt Enable
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB30 : mailbox 30 Interrupt Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB31 : mailbox 31 Interrupt Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.


MIER_FIFO

Mailbox Interrupt Enable Register for FIFO Mailbox Mode
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : MIER
reset_Mask : 0x0

MIER_FIFO MIER_FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 MB8 MB9 MB10 MB11 MB12 MB13 MB14 MB15 MB16 MB17 MB18 MB19 MB20 MB21 MB22 MB23 MB24 MB25 MB28 MB29

MB0 : mailbox 0 Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB1 : mailbox 1 Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB2 : mailbox 2 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB3 : mailbox 3 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB4 : mailbox 4 Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB5 : mailbox 5 Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB6 : mailbox 6 Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB7 : mailbox 7 Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB8 : mailbox 8 Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB9 : mailbox 9 Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB10 : mailbox 10 Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB11 : mailbox 11 Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB12 : mailbox 12 Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB13 : mailbox 13 Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB14 : mailbox 14 Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB15 : mailbox 15 Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB16 : mailbox 16 Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB17 : mailbox 17 Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB18 : mailbox 18 Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB19 : mailbox 19 Interrupt Enable
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB20 : mailbox 20 Interrupt Enable
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB21 : mailbox 21 Interrupt Enable
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB22 : mailbox 22 Interrupt Enable
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB23 : mailbox 23 Interrupt Enable
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB24 : Transmit FIFO Interrupt Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB25 : Transmit FIFO Interrupt Generation Timing Control
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Every time transmission is completed

#1 : 1

When the transmit FIFO becomes empty due to completion of transmission

End of enumeration elements list.

MB28 : Receive FIFO Interrupt Enable
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

MB29 : Receive FIFO Interrupt Generation Timing Control
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Every time reception is completed

#1 : 1

When the receive FIFO becomes buffer warning by completion of reception

End of enumeration elements list.


MCTL_TX0

Message Control Register for Transmit
address_offset : 0x820 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX0 MCTL_TX0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX0

Message Control Register for Receive
address_offset : 0x820 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX0 MCTL_RX0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX1

Message Control Register for Transmit
address_offset : 0x821 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX1 MCTL_TX1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX1

Message Control Register for Receive
address_offset : 0x821 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX1 MCTL_RX1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX2

Message Control Register for Transmit
address_offset : 0x822 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX2 MCTL_TX2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX2

Message Control Register for Receive
address_offset : 0x822 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX2 MCTL_RX2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX3

Message Control Register for Transmit
address_offset : 0x823 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX3 MCTL_TX3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX3

Message Control Register for Receive
address_offset : 0x823 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX3 MCTL_RX3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX4

Message Control Register for Transmit
address_offset : 0x824 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX4 MCTL_TX4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX4

Message Control Register for Receive
address_offset : 0x824 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX4 MCTL_RX4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX5

Message Control Register for Transmit
address_offset : 0x825 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX5 MCTL_TX5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX5

Message Control Register for Receive
address_offset : 0x825 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX5 MCTL_RX5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX6

Message Control Register for Transmit
address_offset : 0x826 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX6 MCTL_TX6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX6

Message Control Register for Receive
address_offset : 0x826 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX6 MCTL_RX6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX7

Message Control Register for Transmit
address_offset : 0x827 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX7 MCTL_TX7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX7

Message Control Register for Receive
address_offset : 0x827 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX7 MCTL_RX7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX8

Message Control Register for Transmit
address_offset : 0x828 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX8 MCTL_TX8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX8

Message Control Register for Receive
address_offset : 0x828 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX8 MCTL_RX8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX9

Message Control Register for Transmit
address_offset : 0x829 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX9 MCTL_TX9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX9

Message Control Register for Receive
address_offset : 0x829 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX9 MCTL_RX9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX10

Message Control Register for Transmit
address_offset : 0x82A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX10 MCTL_TX10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX10

Message Control Register for Receive
address_offset : 0x82A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX10 MCTL_RX10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX11

Message Control Register for Transmit
address_offset : 0x82B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX11 MCTL_TX11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX11

Message Control Register for Receive
address_offset : 0x82B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX11 MCTL_RX11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX12

Message Control Register for Transmit
address_offset : 0x82C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX12 MCTL_TX12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX12

Message Control Register for Receive
address_offset : 0x82C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX12 MCTL_RX12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX13

Message Control Register for Transmit
address_offset : 0x82D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX13 MCTL_TX13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX13

Message Control Register for Receive
address_offset : 0x82D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX13 MCTL_RX13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX14

Message Control Register for Transmit
address_offset : 0x82E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX14 MCTL_TX14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX14

Message Control Register for Receive
address_offset : 0x82E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX14 MCTL_RX14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX15

Message Control Register for Transmit
address_offset : 0x82F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX15 MCTL_TX15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX15

Message Control Register for Receive
address_offset : 0x82F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX15 MCTL_RX15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX16

Message Control Register for Transmit
address_offset : 0x830 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX16 MCTL_TX16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX16

Message Control Register for Receive
address_offset : 0x830 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX16 MCTL_RX16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX17

Message Control Register for Transmit
address_offset : 0x831 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX17 MCTL_TX17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX17

Message Control Register for Receive
address_offset : 0x831 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX17 MCTL_RX17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX18

Message Control Register for Transmit
address_offset : 0x832 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX18 MCTL_TX18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX18

Message Control Register for Receive
address_offset : 0x832 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX18 MCTL_RX18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX19

Message Control Register for Transmit
address_offset : 0x833 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX19 MCTL_TX19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX19

Message Control Register for Receive
address_offset : 0x833 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX19 MCTL_RX19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX20

Message Control Register for Transmit
address_offset : 0x834 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX20 MCTL_TX20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX20

Message Control Register for Receive
address_offset : 0x834 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX20 MCTL_RX20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX21

Message Control Register for Transmit
address_offset : 0x835 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX21 MCTL_TX21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX21

Message Control Register for Receive
address_offset : 0x835 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX21 MCTL_RX21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX22

Message Control Register for Transmit
address_offset : 0x836 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX22 MCTL_TX22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX22

Message Control Register for Receive
address_offset : 0x836 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX22 MCTL_RX22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX23

Message Control Register for Transmit
address_offset : 0x837 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX23 MCTL_TX23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX23

Message Control Register for Receive
address_offset : 0x837 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX23 MCTL_RX23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX24

Message Control Register for Transmit
address_offset : 0x838 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX24 MCTL_TX24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX24

Message Control Register for Receive
address_offset : 0x838 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX24 MCTL_RX24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX25

Message Control Register for Transmit
address_offset : 0x839 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX25 MCTL_TX25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX25

Message Control Register for Receive
address_offset : 0x839 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX25 MCTL_RX25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX26

Message Control Register for Transmit
address_offset : 0x83A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX26 MCTL_TX26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX26

Message Control Register for Receive
address_offset : 0x83A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX26 MCTL_RX26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX27

Message Control Register for Transmit
address_offset : 0x83B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX27 MCTL_TX27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX27

Message Control Register for Receive
address_offset : 0x83B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX27 MCTL_RX27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX28

Message Control Register for Transmit
address_offset : 0x83C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX28 MCTL_TX28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX28

Message Control Register for Receive
address_offset : 0x83C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX28 MCTL_RX28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX29

Message Control Register for Transmit
address_offset : 0x83D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX29 MCTL_TX29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX29

Message Control Register for Receive
address_offset : 0x83D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX29 MCTL_RX29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX30

Message Control Register for Transmit
address_offset : 0x83E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX30 MCTL_TX30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX30

Message Control Register for Receive
address_offset : 0x83E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX30 MCTL_RX30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_TX31

Message Control Register for Transmit
address_offset : 0x83F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL_TX31 MCTL_TX31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SENTDATA TRMACTIVE TRMABT ONESHOT RECREQ TRMREQ

SENTDATA : Transmission Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission is not completed

#1 : 1

Transmission is completed

End of enumeration elements list.

TRMACTIVE : Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmission is pending or transmission is not requested

#1 : 1

From acceptance of transmission request to completion of transmission, or error/arbitration-lost

End of enumeration elements list.

TRMABT : Transmission Abort Complete Flag (Transmit mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested

#1 : 1

Transmission abort is completed

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


MCTL_RX31

Message Control Register for Receive
address_offset : 0x83F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : MCTL_TX[%s]
reset_Mask : 0x0

MCTL_RX31 MCTL_RX31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NEWDATA INVALDATA MSGLOST ONESHOT RECREQ TRMREQ

NEWDATA : Reception Complete Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No data has been received or 0 is written to the NEWDATA bit

#1 : 1

A new message is being stored or has been stored to the mailbox

End of enumeration elements list.

INVALDATA : Reception-in-Progress Status Flag (Receive mailbox setting enabled)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Message valid

#1 : 1

Message being updated

End of enumeration elements list.

MSGLOST : Message Lost Flag(Receive mailbox setting enabled)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Message is not overwritten or overrun

#1 : 1

Message is overwritten or overrun

End of enumeration elements list.

ONESHOT : One-Shot Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

One-shot reception or one-shot transmission disabled

#1 : 1

One-shot reception or one-shot transmission enabled

End of enumeration elements list.

RECREQ : Receive Mailbox Request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for reception

#1 : 1

Configured for reception

End of enumeration elements list.

TRMREQ : Transmit Mailbox Request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not configured for transmission

#1 : 1

Configured for transmission

End of enumeration elements list.


CTLR

Control Register
address_offset : 0x840 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBM IDFM MLM TPM TSRC TSPS CANM SLPM BOM RBOC

MBM : CAN Mailbox Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mailbox mode

#1 : 1

FIFO mailbox mode

End of enumeration elements list.

IDFM : ID Format Mode Select
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#00 : 00

Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids.

#01 : 01

Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs.

#10 : 10

Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO.

#11 : 11

Do not use this combination

End of enumeration elements list.

MLM : Message Lost Mode Select
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Overwrite mode

#1 : 1

Overrun mode

End of enumeration elements list.

TPM : Transmission Priority Mode Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

ID priority transmit mode

#1 : 1

Mailbox number priority transmit mode

End of enumeration elements list.

TSRC : Time Stamp Counter Reset Command
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Nothing occurred

#1 : 1

Reset

End of enumeration elements list.

TSPS : Time Stamp Prescaler Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Every bit time

#01 : 01

Every 2-bit time

#10 : 10

Every 4-bit time

#11 : 11

Every 8-bit time

End of enumeration elements list.

CANM : CAN Operating Mode Select
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : 00

CAN operation mode

#01 : 01

CAN reset mode

#10 : 10

CAN halt mode

#11 : 11

CAN reset mode (forcible transition)

End of enumeration elements list.

SLPM : CAN Sleep Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Other than CAN sleep mode

#1 : 1

CAN sleep mode

End of enumeration elements list.

BOM : Bus-Off Recovery Mode by a program request
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#00 : 00

Normal mode (ISO11898-1 compliant)

#01 : 01

Entry to CAN halt mode automatically at bus-off entry

#10 : 10

Entry to CAN halt mode automatically at bus-off end

#11 : 11

Entry to CAN halt mode (during bus-off recovery period)

End of enumeration elements list.

RBOC : Forcible Return From Bus-Off
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Nothing occurred

#1 : 1

Forcible return from bus-off

End of enumeration elements list.


STR

Status Register
address_offset : 0x842 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR STR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDST SDST RFST TFST NMLST FMLST TABST EST RSTST HLTST SLPST EPST BOST TRMST RECST

NDST : NEWDATA Status Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No mailbox with NEWDATA bit = 1

#1 : 1

Mailbox(es) with NEWDATA bit = 1

End of enumeration elements list.

SDST : SENTDATA Status Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No mailbox with SENTDATA bit = 1

#1 : 1

Mailbox(es) with SENTDATA bit = 1

End of enumeration elements list.

RFST : Receive FIFO Status Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No message in receive FIFO (empty)

#1 : 1

Message in receive FIFO

End of enumeration elements list.

TFST : Transmit FIFO Status Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmit FIFO is full

#1 : 1

Transmit FIFO is not full

End of enumeration elements list.

NMLST : Normal Mailbox Message Lost Status Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No mailbox with MSGLOST bit = 1

#1 : 1

Mailbox(es) with MSGLOST bit = 1

End of enumeration elements list.

FMLST : FIFO Mailbox Message Lost Status Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

RFMLF bit = 0

#1 : 1

RFMLF bit = 1

End of enumeration elements list.

TABST : Transmission Abort Status Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

No mailbox with TRMABT bit = 1

#1 : 1

Mailbox(es) with TRMABT bit = 1

End of enumeration elements list.

EST : Error Status Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

RSTST : CAN Reset Status Flag
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

Not in CAN reset mode

#1 : 1

In CAN reset mode

End of enumeration elements list.

HLTST : CAN Halt Status Flag
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : 0

Not in CAN halt mode

#1 : 1

In CAN halt mode

End of enumeration elements list.

SLPST : CAN Sleep Status Flag
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : 0

Not in CAN sleep mode

#1 : 1

In CAN sleep mode

End of enumeration elements list.

EPST : Error-Passive Status Flag
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

#0 : 0

Not in error-passive state

#1 : 1

In error-passive state

End of enumeration elements list.

BOST : Bus-Off Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Not in bus-off state

#1 : 1

In bus-off state

End of enumeration elements list.

TRMST : Transmit Status Flag (transmitter)
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : 0

Bus idle or reception in progress

#1 : 1

Transmission in progress or in bus-off state

End of enumeration elements list.

RECST : Receive Status Flag (receiver)
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

Bus idle or transmission in progress

#1 : 1

Reception in progress

End of enumeration elements list.


BCR

Bit Configuration Register
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR BCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCLKS TSEG2 SJW BRP TSEG1

CCLKS : CAN Clock Source Selection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

PCLK (generated by the PLL clock)

#1 : 1

CANMCLK (generated by the main clock)

End of enumeration elements list.

TSEG2 : Time Segment 2 Control
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Setting prohibited

#001 : 001

2 Tq

#010 : 010

3 Tq

#011 : 011

4 Tq

#100 : 100

5 Tq

#101 : 101

6 Tq

#110 : 110

7 Tq

#111 : 111

8 Tq

End of enumeration elements list.

SJW : Resynchronization Jump Width Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : 00

1 Tq

#01 : 01

2 Tq

#10 : 10

3 Tq

#11 : 11

4 Tq

End of enumeration elements list.

BRP : Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK).
bits : 16 - 24 (9 bit)
access : read-write

TSEG1 : Time Segment 1 Control
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Setting prohibited

#0001 : 0001

Setting prohibited

#0010 : 0010

Setting prohibited

#0011 : 0011

4 Tq

#0100 : 0100

5 Tq

#0101 : 0101

6 Tq

#0110 : 0110

7 Tq

#0111 : 0111

8 Tq

#1000 : 1000

9 Tq

#1001 : 1001

10 Tq

#1010 : 1010

11 Tq

#1011 : 1011

12 Tq

#1100 : 1100

13 Tq

#1101 : 1101

14 Tq

#1110 : 1110

15 Tq

#1111 : 1111

16 Tq

End of enumeration elements list.


RFCR

Receive FIFO Control Register
address_offset : 0x848 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFCR RFCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RFE RFUST RFMLF RFFST RFWST RFEST

RFE : Receive FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Receive FIFO disabled

#1 : 1

Receive FIFO enabled

End of enumeration elements list.

RFUST : Receive FIFO Unread Message Number Status
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

#000 : 000

No unread message

#001 : 001

1 unread message

#010 : 010

2 unread messages

#011 : 011

3 unread messages

#100 : 100

4 unread messages

: others

Setting prohibited

End of enumeration elements list.

RFMLF : Receive FIFO Message Lost Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No receive FIFO message lost has occurred

#1 : 1

Receive FIFO message lost has occurred

End of enumeration elements list.

RFFST : Receive FIFO Full Status Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Receive FIFO is not full

#1 : 1

Receive FIFO is full (4 unread messages)

End of enumeration elements list.

RFWST : Receive FIFO Buffer Warning Status Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

Receive FIFO is not buffer warning

#1 : 1

Receive FIFO is buffer warning (3 unread messages)

End of enumeration elements list.

RFEST : Receive FIFO Empty Status Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

Unread message in receive FIFO

#1 : 1

No unread message in receive FIFO

End of enumeration elements list.


RFPCR

Receive FIFO Pointer Control Register
address_offset : 0x849 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RFPCR RFPCR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RFPCR

RFPCR : The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR.
bits : 0 - 6 (7 bit)
access : write-only


TFCR

Transmit FIFO Control Register
address_offset : 0x84A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFCR TFCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TFE TFUST TFFST TFEST

TFE : Transmit FIFO Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmit FIFO disabled

#1 : 1

Transmit FIFO enabled

End of enumeration elements list.

TFUST : Transmit FIFO Unsent Message Number Status
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

#000 : 000

No unsent message

#001 : 001

1 unsent message

#010 : 010

2 unsent messages

#011 : 011

3 unsent messages

#100 : 100

4 unsent messages

: others

Setting prohibited

End of enumeration elements list.

TFFST : Transmit FIFO Full Status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transmit FIFO is not full

#1 : 1

Transmit FIFO is full (4 unsent messages)

End of enumeration elements list.

TFEST : Transmit FIFO Empty Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

Unsent message in transmit FIFO

#1 : 1

No unsent message in transmit FIFO

End of enumeration elements list.


TFPCR

Transmit FIFO Pointer Control Register
address_offset : 0x84B Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TFPCR TFPCR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TFPCR

TFPCR : The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR.
bits : 0 - 6 (7 bit)
access : write-only


EIER

Error Interrupt Enable Register
address_offset : 0x84C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EIER EIER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BEIE EWIE EPIE BOEIE BORIE ORIE OLIE BLIE

BEIE : Bus Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error interrupt disabled

#1 : 1

Bus error interrupt enabled

End of enumeration elements list.

EWIE : Error-Warning Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Error-warning interrupt disabled

#1 : 1

Error-warning interrupt enabled

End of enumeration elements list.

EPIE : Error-Passive Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Error-passive interrupt disabled

#1 : 1

Error-passive interrupt enabled

End of enumeration elements list.

BOEIE : Bus-Off Entry Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus-off entry interrupt disabled

#1 : 1

Bus-off entry interrupt enabled

End of enumeration elements list.

BORIE : Bus-Off Recovery Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus-off recovery interrupt disabled

#1 : 1

Bus-off recovery interrupt enabled

End of enumeration elements list.

ORIE : Overrun Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Receive overrun interrupt disabled

#1 : 1

Receive overrun interrupt enabled

End of enumeration elements list.

OLIE : Overload Frame Transmit Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Overload frame transmit interrupt disabled

#1 : 1

Overload frame transmit interrupt enabled

End of enumeration elements list.

BLIE : Bus Lock Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus lock interrupt disabled

#1 : 1

Bus lock interrupt enabled

End of enumeration elements list.


EIFR

Error Interrupt Factor Judge Register
address_offset : 0x84D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EIFR EIFR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BEIF EWIF EPIF BOEIF BORIF ORIF OLIF BLIF

BEIF : Bus Error Detect Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No bus error detected

#1 : 1

Bus error detected

End of enumeration elements list.

EWIF : Error-Warning Detect Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

No error-warning detected

#1 : 1

Error-warning detected

End of enumeration elements list.

EPIF : Error-Passive Detect Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No error-passive detected

#1 : 1

Error-passive detected

End of enumeration elements list.

BOEIF : Bus-Off Entry Detect Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No bus-off entry detected

#1 : 1

Bus-off entry detected

End of enumeration elements list.

BORIF : Bus-Off Recovery Detect Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No bus-off recovery detected

#1 : 1

Bus-off recovery detected

End of enumeration elements list.

ORIF : Receive Overrun Detect Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

No receive overrun detected

#1 : 1

Receive overrun detected

End of enumeration elements list.

OLIF : Overload Frame Transmission Detect Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No overload frame transmission detected

#1 : 1

Overload frame transmission detected

End of enumeration elements list.

BLIF : Bus Lock Detect Flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

No bus lock detected

#1 : 1

Bus lock detected

End of enumeration elements list.


RECR

Receive Error Count Register
address_offset : 0x84E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RECR RECR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RECR

RECR : Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception.
bits : 0 - 6 (7 bit)
access : read-only


TECR

Transmit Error Count Register
address_offset : 0x84F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TECR TECR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TECR

TECR : Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission.
bits : 0 - 6 (7 bit)
access : read-only


ECSR

Error Code Store Register
address_offset : 0x850 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECSR ECSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEF FEF AEF CEF BE1F BE0F ADEF EDPM

SEF : Stuff Error Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No stuff error detected

#1 : 1

Stuff error detected

End of enumeration elements list.

FEF : Form Error Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

No form error detected

#1 : 1

Form error detected

End of enumeration elements list.

AEF : ACK Error Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No ACK error detected

#1 : 1

ACK error detected

End of enumeration elements list.

CEF : CRC Error Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No CRC error detected

#1 : 1

CRC error detected

End of enumeration elements list.

BE1F : Bit Error (recessive) Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No bit error (recessive) detected

#1 : 1

Bit error (recessive) detected

End of enumeration elements list.

BE0F : Bit Error (dominant) Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

No bit error (dominant) detected

#1 : 1

Bit error (dominant) detected

End of enumeration elements list.

ADEF : ACK Delimiter Error Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No ACK delimiter error detected

#1 : 1

ACK delimiter error detected

End of enumeration elements list.

EDPM : Error Display Mode Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output of first detected error code

#1 : 1

Output of accumulated error code

End of enumeration elements list.


CSSR

Channel Search Support Register
address_offset : 0x851 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSSR CSSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CSSR

CSSR : When the value for the channel search is input, the channel number is output to MSSR.
bits : 0 - 6 (7 bit)
access : read-write


MSSR

Mailbox Search Status Register
address_offset : 0x852 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSSR MSSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MBNST SEST

MBNST : Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR.
bits : 0 - 3 (4 bit)
access : read-only

SEST : Search Result Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

Search result found

#1 : 1

No search result

End of enumeration elements list.


MSMR

Mailbox Search Mode Register
address_offset : 0x853 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSMR MSMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MBSM

MBSM : Mailbox Search Mode Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Receive mailbox search mode

#01 : 01

Transmit mailbox search mode

#10 : 10

Message lost search mode

#11 : 11

Channel search mode

End of enumeration elements list.


TSR

Time Stamp Register
address_offset : 0x854 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSR

TSR : Free-running counter value for the time stamp function
bits : 0 - 14 (15 bit)
access : read-only


AFSR

Acceptance Filter Support Register
address_offset : 0x856 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFSR AFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFSR

AFSR : After the standard ID of a received message is written, the value converted for data table search can be read.
bits : 0 - 14 (15 bit)
access : read-write


TCR

Test Control Register
address_offset : 0x858 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TSTE TSTM

TSTE : CAN Test Mode Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

CAN test mode disabled

#1 : 1

CAN test mode enabled

End of enumeration elements list.

TSTM : CAN Test Mode Select
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#00 : 00

Other than CAN test mode

#01 : 01

Listen-only mode

#10 : 10

Self-test mode 0 (external loopback)

#11 : 11

Self-test mode 1 (internal loopback)

End of enumeration elements list.



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