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QSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x800 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

SFMSMD

SFMCOM

SFMCMD

SFMCST

SFMSIC

SFMSAC

SFMSDC

SFMSPC

SFMPMD

SFMSSC

SFMSKC

SFMCNT1

SFMSST


SFMSMD

Transfer Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSMD SFMSMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMRM SFMSE SFMPFE SFMPAE SFMMD3 SFMOEX SFMOHW SFMOSW SFMCCE

SFMRM : Serial interface read mode selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

Standard Read

#001 : 001

Fast Read

#010 : 010

Fast Read Dual Output

#011 : 011

Fast Read Dual I/O

#100 : 100

Fast Read Quad Output

#101 : 101

Fast Read Quad I/O

#110 : 110

Setting prohibited

#111 : 111

Setting prohibited

End of enumeration elements list.

SFMSE : Selection of the prefetch function
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

Does not extend QSSL

#01 : 01

Extends QSSL by 33*QSPCLK

#10 : 10

Extends QSSL by 129*QSPCLK

#11 : 11

Extends QSSL infinitely

End of enumeration elements list.

SFMPFE : Selection of the prefetch function
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables prefetch

#1 : 1

Enables prefetch

End of enumeration elements list.

SFMPAE : Selection of the function for stopping prefetch at locations other than on byte boundaries
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables prefetch stopping at locations other than on byte boundaries

#1 : 1

Enables prefetch stopping at locations other than on byte boundaries

End of enumeration elements list.

SFMMD3 : SPI mode selection. An initial value is determined by input to CFGMD3.
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

SPI mode 0

#1 : 1

SPI mode 3

End of enumeration elements list.

SFMOEX : Extension of the I/O buffer output enable signal for the serial interface
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not extend the output enable signal

#1 : 1

Extends the output enable signal by 1*QSPCLK

End of enumeration elements list.

SFMOHW : Hold time adjustment for serial transmission
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not extend the high-level width of SCK at transmission time

#1 : 1

Extends the high-level width of SCK by 1*PCLKA at transmission time

End of enumeration elements list.

SFMOSW : Setup time adjustment for serial transmission
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not extend the low-level width of SCK at transmission time

#1 : 1

Extends the low-level width of SCK by 1*PCLKA at transmission time

End of enumeration elements list.

SFMCCE : Read instruction code selection.
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Default instruction code set for each instruction

#1 : 1

Instruction code written in the SFMSIC register

End of enumeration elements list.


SFMCOM

Communication Port Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMCOM SFMCOM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMD

SFMD : Port for direct communication with the SPI bus.Input/output to and from this port is converted to an SPI bus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode.
bits : 0 - 6 (7 bit)
access : read-write


SFMCMD

Communication Mode Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMCMD SFMCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCOM

DCOM : Selection of a mode of communication with the SPI bus
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

ROM access mode

#1 : 1

Direct communication mode

End of enumeration elements list.


SFMCST

Communication Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMCST SFMCST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMBSY EROMR

COMBSY : SPI bus cycle completion state in direct communication
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

There is no serial transfer being processed.

#1 : 1

There is a serial transfer being processed.

End of enumeration elements list.

EROMR : Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored.
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

ROM access is not detected in direct communication mode

#1 : 1

ROM access is detected in direct communication mode

End of enumeration elements list.


SFMSIC

Instruction Code Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSIC SFMSIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMCIC

SFMCIC : Serial ROM instruction code to substitute
bits : 0 - 6 (7 bit)
access : read-write


SFMSAC

Address Mode Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSAC SFMSAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMAS SFM4BC

SFMAS : Selection the number of address bits of the serial interface
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

1byte

#01 : 01

2bytes

#10 : 10

3bytes

#11 : 11

4 bytes

End of enumeration elements list.

SFM4BC : Selection of a default instruction code, when Serial Interface address width is selected 4 bytes.
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not use 4 Byte address read Instruction code

#1 : 1

Use 4 Byte address read Instruction code

End of enumeration elements list.


SFMSDC

Dummy Cycle Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSDC SFMSDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMDN SFMXST SFMXEN SFMXD

SFMDN : Selection of the number of dummy cycles of Fast Read instructions
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Default dummy cycles of each instruction.

: others

( SFMDN + 2 ) x SCK

End of enumeration elements list.

SFMXST : XIP mode status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

Normal (non-XIP) mode is operating

#1 : 1

XIP mode is operating

End of enumeration elements list.

SFMXEN : XIP mode permission
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

XIP mode is prohibited

#1 : 1

XIP mode is permitted

End of enumeration elements list.

SFMXD : Mode data for serial ROM. (Control XIP mode)
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

#0 : 0

XIP mode is prohibited

#1 : 1

XIP mode is permitted

End of enumeration elements list.


SFMSPC

SPI Protocol Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSPC SFMSPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMSPI SFMSDE

SFMSPI : Selection of SPI protocolNOTE: Serial ROM's SPI protocol is required to be set by software separately.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Extended SPI protocol

#01 : 01

Dual SPI protocol

#10 : 10

Quad SPI protocol

#11 : 11

Setting prohibited.

End of enumeration elements list.

SFMSDE : Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected.
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not allocate minimum switch time

#1 : 1

Allocate the minimum switch time equivalent to 1*QSPXLK

End of enumeration elements list.


SFMPMD

Port Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMPMD SFMPMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMWPL

SFMWPL : Specify level of WP pin
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Low level

#1 : 1

High level

End of enumeration elements list.


SFMSSC

Chip Selection Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSSC SFMSSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMSW SFMSHD SFMSLD

SFMSW : Selection of a minimum high-level width of the QSSL signal
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

1 x QSPCLK

#0001 : 0001

2 x QSPCLK

#0010 : 0010

3 x QSPCLK

#0011 : 0011

4 x QSPCLK

#0100 : 0100

5 x QSPCLK

#0101 : 0101

6 x QSPCLK

#0110 : 0110

7 x QSPCLK

#0111 : 0111

8 x QSPCLK

#1000 : 1000

9 x QSPCLK

#1001 : 1001

10 x QSPCLK

#1010 : 1010

11 x QSPCLK

#1011 : 1011

12 x QSPCLK

#1100 : 1100

13 x QSPCLK

#1101 : 1101

14 x QSPCLK

#1110 : 1110

15 x QSPCLK

#1111 : 1111

16 x QSPCLK

End of enumeration elements list.

SFMSHD : QSSL signal release timing selection
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Releases QSSL 0.5*SCK after the last rising edge of QSPCLK

#1 : 1

Releases QSSL 1.5*SCK after the last rising edge of QSPCLK

End of enumeration elements list.

SFMSLD : QSSL signal output timing selection
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK

#1 : 1

Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK

End of enumeration elements list.


SFMSKC

Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSKC SFMSKC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMDV SFMDTY

SFMDV : Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#10000 : 10000

18 x PCLKA

#10001 : 10001

20 x PCLKA

#10010 : 10010

22 x PCLKA

#10011 : 10011

24 x PCLKA

#10100 : 10100

26 x PCLKA

#10101 : 10101

28 x PCLKA

#10110 : 10110

30 x PCLKA

#10111 : 10111

32 x PCLKA

#11000 : 11000

34 x PCLKA

#11001 : 11001

36 x PCLKA

#11010 : 11010

38 x PCLKA

#11011 : 11011

40 x PCLKA

#11100 : 11100

42 x PCLKA

#11101 : 11101

44 x PCLKA

#11110 : 11110

46 x PCLKA

#11111 : 11111

48 x PCLKA

: others

( SFMDV + 2 ) x PCLKA

End of enumeration elements list.

SFMDTY : Selection of a duty ratio correction function for the SCK signal
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Serial interface reference cycle selection (* Pay attention to the irregularity.)

#1 : 1

Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number)

End of enumeration elements list.


SFMCNT1

External QSPI Address Register 1
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMCNT1 SFMCNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPI_EXT

QSPI_EXT : BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.
bits : 26 - 30 (5 bit)
access : read-write


SFMSST

Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SFMSST SFMSST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PFCNT PFFUL PFOFF

PFCNT : Number of bytes of prefetched dataRange: 00000 - 10010 (No combination other than the above is available.)
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

#00000 : 00000

Nodata has been prefetched.

: others

Data of (PFCNT) bytes hs been prefetched.

End of enumeration elements list.

PFFUL : Prefetch buffer state
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

The prefetch buffer has a free space.

#1 : 1

The prefetch buffer is full.

End of enumeration elements list.

PFOFF : Prefetch function operation state
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

The prefetch function is operating.

#1 : 1

The prefetch function is not enabled or is not operating.

End of enumeration elements list.



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