Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
Input Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SRCID : SRCID is a 32-bit writ-only register that is used to input the data before sampling rate conversion. All the bits are read as 0.
bits : 0 - 30 (31 bit)
access : write-only
Output Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRCOD : SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again.
bits : 0 - 30 (31 bit)
access : read-only
Input Data Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFTRG : Input FIFO Data Triggering Number
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
0
#01 : 01
2
#10 : 10
4
#11 : 11
6
End of enumeration elements list.
IEN : Input FIFO Empty Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Input FIFO empty interrupt is disabled.
#1 : 1
Input FIFO empty interrupt is enabled.
End of enumeration elements list.
IED : Input Data Endian
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Endian formats 1 are the same between the CPU and input data.
#1 : 1
Endian formats 1 are different between the CPU and input data.
End of enumeration elements list.
Output Data Control Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFTRG : Output FIFO Data Trigger Number
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
1
#01 : 01
4
#10 : 10
8
#11 : 11
12
End of enumeration elements list.
OEN : Output Data FIFO Full Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output data FIFO full interrupt is disabled.
#1 : 1
Output data FIFO full interrupt is enabled.
End of enumeration elements list.
OED : Output Data Endian
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Endian formats are the same between the chip and input data.
#1 : 1
Endian formats are different between the chip and input data.
End of enumeration elements list.
OCH : Output Data Channel Exchange
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not exchange the channels (the same order as data input)
#1 : 1
Exchanges the channels (the opposite order from data input)
End of enumeration elements list.
Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFS : Output Sampling Rate
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
44.1 kHz
#001 : 001
48.0 kHz
#010 : 010
32.0 kHz
#011 : 011
Setting prohibited
#100 : 100
8.0 kHz ( Valid only when IFS[3:0] =1001b )
#101 : 101
16.0 kHz ( Valid only when IFS[3:0] =1001b )
: others
Settings other than above are prohibited.
End of enumeration elements list.
IFS : Input Sampling Rate
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
8.0 kHz
#0001 : 0001
11.025 kHz
#0010 : 0010
12.0 kHz
#0011 : 0011
Setting prohibited
#0100 : 0100
16.0 kHz
#0101 : 0101
22.05 kHz
#0110 : 0110
24.0 kHz
#0111 : 0111
Setting prohibited
#1000 : 1000
32.0 kHz
#1001 : 1001
44.1 kHz
#1010 : 1010
48.0 kHz
: others
Settings prohibited.
End of enumeration elements list.
CL : Internal Work Memory Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
Clears the input FIFO, output FIFO, input buffer memory, intermediate memory and accumulator.
End of enumeration elements list.
FL : Internal Work Memory Flush
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory(i.e., flush processing).
End of enumeration elements list.
OVEN : Output Data FIFO Overwrite Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output data FIFO overwrite interrupt is disabled.
#1 : 1
Output data FIFO overwrite interrupt is enabled.
End of enumeration elements list.
UDEN : Output Data FIFO Underflow Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables output data FIFO underflow interrupt requests.
#1 : 1
Enables output data FIFO underflow interrupt requests.
End of enumeration elements list.
SRCEN : Module Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables this module operation.
#1 : 1
Enables this module operation.
End of enumeration elements list.
CEEN : Conversion End Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables conversion end interrupt requests.
#1 : 1
Enables conversion end interrupt requests.
End of enumeration elements list.
FICRAE : Filter Coefficient Table Access Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reading/writing to filter coefficient table RAM is disabled.
#1 : 1
Reading/writing to filter coefficient table RAM is enabled.
End of enumeration elements list.
Status Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OINT : Output Data FIFO Full Interrupt Request Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Number of data units in the output FIFO has not become equal to or greater than the specified triggering number.
#1 : 1
Number of data units in the output FIFO has become equal to or greater than the specified triggering number.
End of enumeration elements list.
IINT : Input Data FIFO Empty Interrupt Request Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Number of data units in the input FIFO has not become equal to or smaller than the specified triggering number.
#1 : 1
Number of data units in the input FIFO has become equal to or smaller than the specified triggering number.
End of enumeration elements list.
OVF : Output Data FIFO Overwrite Interrupt Request Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Next data conversion processing is not completed.
#1 : 1
Next data conversion processing is completed.
End of enumeration elements list.
UDF : Output FIFO Underflow Interrupt Request Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output data FIFO has not been read out.
#1 : 1
Output data FIFO has been read out.
End of enumeration elements list.
FLF : Flush Processing Status Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Flash processing is completed.
#1 : 1
Flash processing is in progress.
End of enumeration elements list.
CEF : Conversion End Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
All of the output data has not been read out.
#1 : 1
All of the output data has been read out.
End of enumeration elements list.
IFDN : Input FIFO Data Count
bits : 7 - 9 (3 bit)
access : read-only
Enumeration:
: IFDN
The value of IFDN indicatethe number of data units in the input FIFO.
End of enumeration elements list.
OFDN : Output FIFO Data Count
bits : 11 - 14 (4 bit)
access : read-only
Enumeration:
: OFDN
The value of OFDN indicatethe number of data units in the output FIFO.
End of enumeration elements list.
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