\n

DBG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

DBGSTR

DBGSTOPCR

TRACECTR


DBGSTR

Debug Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBGSTR DBGSTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDBGPWRUPREQ CDBGPWRUPACK

CDBGPWRUPREQ : Debug power-up request
bits : 28 - 27 (0 bit)
access : read-only

Enumeration:

#0 : 0

OCD is not requesting debug power-up

#1 : 1

OCD is requesting debug power-up

End of enumeration elements list.

CDBGPWRUPACK : Debug power-up acknowledge
bits : 29 - 28 (0 bit)
access : read-only

Enumeration:

#0 : 0

Debug power-up request is not acknowledged

#1 : 1

Debug power-up request is acknowledged

End of enumeration elements list.


DBGSTOPCR

Debug Stop Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGSTOPCR DBGSTOPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGSTOP_IWDT DBGSTOP_WDT DBGSTOP_LVD DBGSTOP_RPER DBGSTOP_RECCR

DBGSTOP_IWDT : Mask bit for IWDT reset/interrupt
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask IWDT reset/interrupt

#1 : 1

Enable IWDT reset

End of enumeration elements list.

DBGSTOP_WDT : Mask bit for WDT reset/interrupt
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mask WDT reset/interrupt

#1 : 1

Enable WDT reset

End of enumeration elements list.

DBGSTOP_LVD : b18: Mask bit for LVD2 reset/interrupt (0:enable / 1:Mask)b17: Mask bit for LVD1 reset/interrupt (0:enable / 1:Mask)b16: Mask bit for LVD0 reset (0:enable / 1:Mask)
bits : 16 - 17 (2 bit)
access : read-write

DBGSTOP_RPER : Mask bit for RAM parity error reset/interrupt
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable RAM parity error reset/interrupt

#1 : 1

Mask RAM parity error reset/interrupt

End of enumeration elements list.

DBGSTOP_RECCR : Mask bit for RAM ECC error reset/interrupt
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable RAM ECC error reset/interrupt

#1 : 1

Mask RAM ECC error reset/interrupt

End of enumeration elements list.


TRACECTR

Trace Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRACECTR TRACECTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENETBFULL

ENETBFULL : Enable bit for halt request by ETB full
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

ETB full does not cause CPU halt

#1 : 1

ETB full cause CPU halt

End of enumeration elements list.



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