\n
address_offset : 0x0 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x13 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x18 Bytes (0x0)
size : 0x7 byte (0x0)
mem_usage : registers
protection :
DMA Source Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMSAR : Specifies the transfer source start address.
bits : 0 - 30 (31 bit)
access : read-write
DMA Transfer Mode Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCTG : Transfer Request Source Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Software
#01 : 01
Interrupts from peripheral modules or external interrupt input pins
: others
Setting prohibited
End of enumeration elements list.
SZ : Transfer Data Size Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
8 bits
#01 : 01
16 bits
#10 : 10
32 bits
#11 : 11
Setting prohibited
End of enumeration elements list.
DTS : Repeat Area Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : 00
Specify destination as the repeat area or block area
#01 : 01
Specify source as the repeat area or block area
#10 : 10
Do not specify repeat area or block area
#11 : 11
Setting prohibited
End of enumeration elements list.
MD : Transfer Mode Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Normal transfer
#01 : 01
Repeat transfer
#10 : 10
Block transfer
#11 : 11
Setting prohibited
End of enumeration elements list.
DMA Interrupt Setting Register
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DARIE : Destination Address Extended Repeat Area Overflow Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable.
End of enumeration elements list.
SARIE : Source Address Extended Repeat Area Overflow Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable.
End of enumeration elements list.
RPTIE : Repeat Size End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable.
End of enumeration elements list.
ESIE : Transfer Escape End Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable.
End of enumeration elements list.
DTIE : Transfer End Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable.
End of enumeration elements list.
DMA Address Mode Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DARA : Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings.
bits : 0 - 3 (4 bit)
access : read-write
DM : Destination Address Update Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Fixed address
#01 : 01
Offset addition
#10 : 10
Incremented address
#11 : 11
Decremented address.
End of enumeration elements list.
SARA : Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings.
bits : 8 - 11 (4 bit)
access : read-write
SM : Source Address Update Mode
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Fixed address
#01 : 01
Offset addition
#10 : 10
Incremented address
#11 : 11
Decremented address.
End of enumeration elements list.
DMA Offset Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMOFR : Specifies the offset when offset addition is selected as the address update mode for transfer source or destination.
bits : 0 - 30 (31 bit)
access : read-write
DMA Transfer Enable Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTE : DMA Transfer Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DMA Software Start Register
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWREQ : DMA Software Start
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not request DMA transfer
#1 : 1
Request DMA transfer.
End of enumeration elements list.
CLRS : DMA Software Start Bit Auto Clear Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clear SWREQ bit after DMA transfer is started by software
#1 : 1
Do not clear SWREQ bit after DMA transfer is started by software
End of enumeration elements list.
DMAC Module Activation Register
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESIF : Transfer Escape End Interrupt Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A transfer escape end interrupt has not been generated.
#1 : 1
A transfer escape end interrupt has been generated.
End of enumeration elements list.
DTIF : Transfer End Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt occurred
#1 : 1
Interrupt occurred.
End of enumeration elements list.
ACT : DMA Active Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMAC operation is suspended.
#1 : 1
DMAC is operating.
End of enumeration elements list.
DMA Destination Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMDAR : Specifies the transfer destination start address.
bits : 0 - 30 (31 bit)
access : read-write
DMA Transfer Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMCRAL : Lower bits of transfer count
bits : 0 - 14 (15 bit)
access : read-write
DMCRAH : Upper bits of transfer count
bits : 16 - 24 (9 bit)
access : read-write
DMA Block Transfer Count Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMCRB : Specifies the number of block transfer operations or repeat transfer operations.
bits : 0 - 14 (15 bit)
access : read-write
Enumeration:
#0000 : 0000
65,536 blocks
: others
DMCRB blocks
End of enumeration elements list.
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