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SRAM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC0 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

Registers

PARIOAD

SRAMPRCR

SRAMWTSC

ECCMODE

ECC2STS

ECC1STSEN

ECC1STS

ECCPRCR

ECCETST

ECCOAD


PARIOAD

SRAM Parity Error Operation After Detection Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PARIOAD PARIOAD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OAD

OAD : Operation after Detection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Reset

End of enumeration elements list.


SRAMPRCR

SRAM Protection Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAMPRCR SRAMPRCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SRAMPRCR KW

SRAMPRCR : Register Write Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable writes to protected registers

#1 : 1

Enable writes to protected registers

End of enumeration elements list.

KW : Write Key Code
bits : 1 - 6 (6 bit)
access : write-only

Enumeration:

#1111000 : 1111000

Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b.

: others

Writing to the RAMPRCR bit is invalid.

End of enumeration elements list.


SRAMWTSC

RAM Wait State Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAMWTSC SRAMWTSC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ECCRAMRDWTEN SRAM0WTEN SRAM1WTEN

ECCRAMRDWTEN : ECCRAM Read wait enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not add wait state in read access cycle to SRAM0 (ECC area)

#1 : 1

Add wait state in read access cycle to SRAM0 (ECC area)

End of enumeration elements list.

SRAM0WTEN : SRAM0 Wait Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not add wait state in read access cycle to SRAM0

#1 : 1

Add wait state in read access cycle to SRAM0

End of enumeration elements list.

SRAM1WTEN : SRAM1 Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not add wait state in read access cycle to SRAM1

#1 : 1

Add wait state in read access cycle to SRAM1

End of enumeration elements list.


ECCMODE

ECCRAM Operating Mode Control Register
address_offset : 0xC0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCMODE ECCMODE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ECCMOD

ECCMOD : ECC Operating Mode Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Disable ECC function

#01 : 01

Setting prohibited

#10 : 10

Enable ECC function without error checking

#11 : 11

Enable ECC function with error checking.

End of enumeration elements list.


ECC2STS

ECCRAM 2-Bit Error Status Register
address_offset : 0xC1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC2STS ECC2STS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ECC2ERR

ECC2ERR : ECC 2-Bit Error Status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No 2-bit ECC error occurred

#1 : 1

2-bit ECC error occurred

End of enumeration elements list.


ECC1STSEN

ECCRAM 1-Bit Error Information Update Enable Register
address_offset : 0xC2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC1STSEN ECC1STSEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 E1STSEN

E1STSEN : ECC 1-Bit Error Information Update Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables updating of the 1-bit ECC error information.

#1 : 1

Enables updating of the 1-bit ECC error information.

End of enumeration elements list.


ECC1STS

ECCRAM 1-Bit Error Status Register
address_offset : 0xC3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC1STS ECC1STS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ECC1ERR

ECC1ERR : ECC 1-Bit Error Status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No 1-bit ECC error occurred

#1 : 1

1-bit ECC error occurred

End of enumeration elements list.


ECCPRCR

ECCRAM Protection Register
address_offset : 0xC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCPRCR ECCPRCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ECCPRCR KW

ECCPRCR : ECCRAMETST Register Write Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable writes to protected registers

#1 : 1

Enable writes to protected registers

End of enumeration elements list.

KW : Write Key Code
bits : 1 - 6 (6 bit)
access : write-only

Enumeration:

#1111000 : 1111000

Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b.

: others

Writing to the ECCRAMPRCR bit is invalid.

End of enumeration elements list.


ECCETST

ECC Test Control Register
address_offset : 0xD4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCETST ECCETST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TSTBYP

TSTBYP : ECC Bypass Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

ECC bypass disabled

#1 : 1

ECC bypass enabled.

End of enumeration elements list.


ECCOAD

RAM ECC Error Operation After Detection Register
address_offset : 0xD8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCOAD ECCOAD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OAD

OAD : Operation after Detection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non maskable interrupt.

#1 : 1

Internal reset.

End of enumeration elements list.



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