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FCACHE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x30 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x32 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x11C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x120 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x124 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x127 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x130 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x138 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

Registers

FCACHEE

FCACHEIV

FLWT


FCACHEE

Flash Cache Enable Register
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCACHEE FCACHEE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCACHEEN

FCACHEEN : FCACHE Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

FCACHE is disabled

#1 : 1

FCACHE is enabled

End of enumeration elements list.


FCACHEIV

Flash Cache Invalidate Register
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCACHEIV FCACHEIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCACHEIV

FCACHEIV : FCACHE Invalidation
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

(Read)not in progress / (Write) no effect.

#1 : 1

(Read)in progress /(Write) Starting Cache Invalidation

End of enumeration elements list.


FLWT

Flash Wait Cycle Register
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLWT FLWT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLWT

FLWT : Flash Wait Cycle
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

0 wait (ICLK<=80MHz)

#001 : 001

1 wait (80MHz < ICLK <=160MHz)

#010 : 010

2 waits (160MHz < ICLK <=240MHz)

: others

Setting prohibited

End of enumeration elements list.



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