SYSTEM

PLLMUL : PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 111011: x30.0
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

: others

Setting prohibited

End of enumeration elements list.

PLLCR

PLL Control Register
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSTP : PLL Stop Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the PLL

#1 : 1

Stop the PLL.

End of enumeration elements list.

BCKCR

External Bus Clock Control Register
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCLKDIV : BCLK Pin Output Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

BCLK

#1 : 1

BCLK/2

End of enumeration elements list.

MOSCCR

Main Clock Oscillator Control Register
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOSTP : Main Clock Oscillator Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Main clock oscillator is operating.

#1 : 1

Main clock oscillator is stopped.

End of enumeration elements list.

HOCOCR

High-Speed On-Chip Oscillator Control Register
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCSTP : HOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the HOCO clock

#1 : 1

Stop the HOCO clock

End of enumeration elements list.

MOCOCR

Middle-Speed On-Chip Oscillator Control Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCSTP : MOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the MOCO clock

#1 : 1

Stop the MOCO clock

End of enumeration elements list.

FLLCR1

FLL Control Register 1
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLLEN : FLL Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

FLL function is disabled.

#1 : 1

FLL function is enabled.

End of enumeration elements list.

FLLCR2

FLL Control Register 2
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLLCNTL : FLL Multiplication ControlMultiplication ratio of the FLL reference clock select
bits : 0 - 9 (10 bit)
access : read-write

OSCSF

Oscillation Stabilization Flag Register
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOCOSF : HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1.
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

HOCO clock is stopped or is not yet stable

#1 : 1

HOCO clock is stable, so is available for use as the system clock

End of enumeration elements list.

MOSCSF : Main Clock Oscillation Stabilization Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

Main clock oscillator is stopped (MOSTP = 1) or is not yet stable

#1 : 1

Main clock oscillator is stable, so is available for use as the system clock

End of enumeration elements list.

PLLSF : PLL Clock Oscillation Stabilization Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

PLL clock is stopped or is not yet stable

#1 : 1

PLL clock is stable, so is available for use as the system clock

End of enumeration elements list.

CKOCR

Clock Out Control Register
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKOSEL : Clock out source select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

HOCO

#001 : 001

MOCO

#010 : 010

LOCO

#011 : 011

MOSC

#100 : 100

SOSC

: others

Setting prohibited

End of enumeration elements list.

CKODIV : Clock out input frequency Division Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

#111 : 111

/128

End of enumeration elements list.

CKOEN : Clock out enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable clock out

#1 : 1

Enable clock out

End of enumeration elements list.

TRCKCR

Trace Clock Control Register
address_offset : 0x3F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRCK : Trace Clock operating frequency select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

#0001 : 0001

#0010 : 0010

: others

Setting prohibited

End of enumeration elements list.

TRCKEN : Trace Clock operating Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

PRCR

Protect Register
address_offset : 0x3FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRC0 : Enables writing to the registers related to the clock generation circuit.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writes protected.

#1 : 1

Writes not protected.

End of enumeration elements list.

PRC1 : Enables writing to the registers related to the operating modes, the low power consumption modes and the battery backup function.
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writes protected.

#1 : 1

Writes not protected.

End of enumeration elements list.

PRC3 : Enables writing to the registers related to the LVD.
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writes protected.

#1 : 1

Writes not protected.

End of enumeration elements list.

PRKEY : PRKEY Key Code
bits : 8 - 14 (7 bit)
access : write-only

Enumeration:

0x5A : 0x5A

Enables writing to the PRCR register.

: others

Disables writing to the PRCR register.

End of enumeration elements list.

OSTDCR

Oscillation Stop Detection Control Register
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTDIE : Oscillation Stop Detection Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable oscillation stop detection interrupt (do not notify the POEG)

#1 : 1

Enable oscillation stop detection interrupt (notify the POEG)

End of enumeration elements list.

OSTDE : Oscillation Stop Detection Function Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable oscillation stop detection function

#1 : 1

Enable oscillation stop detection function

End of enumeration elements list.

DPSBYCR

Deep Standby Control Register
address_offset : 0x400 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEEPCUT : Power-Supply Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode.

#01 : 01

Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is not supplied in deep software standby mode.

#10 : 10

Setting prohibited.

#11 : 11

Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled.

End of enumeration elements list.

IOKEEP : I/O Port Retention
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

When the Deep Software Standby mode is canceled, the I/O ports are in the reset state.

#1 : 1

When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode.

End of enumeration elements list.

DPSBY : Deep Software Standby
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1)

#1 : 1

Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1)

End of enumeration elements list.

DPSIER0

Deep Standby Interrupt Enable Register 0
address_offset : 0x402 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ0E : IRQ0-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ1E : IRQ1-DS Pin Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ4E : IRQ4-DS Pin Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ5E : IRQ5-DS Pin Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ6E : IRQ6-DS Pin Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ7E : IRQ7-DS Pin Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DPSIER1

Deep Standby Interrupt Enable Register 1
address_offset : 0x403 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ8E : IRQ8-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ9E : IRQ9-DS Pin Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ10E : IRQ10-DS Pin Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ11E : IRQ11-DS Pin Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ12E : IRQ12-DS Pin Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DPSIER2

Deep Standby Interrupt Enable Register 2
address_offset : 0x404 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLVD1IE : LVD1 Deep Standby Cancel Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DLVD2IE : LVD2 Deep Standby Cancel Signal Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DTRTCIIE : RTC Interval interrupt Deep Standby Cancel Signal Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DRTCAIE : RTC Alarm interrupt Deep Standby Cancel Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DNMIE : NMI Pin Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DPSIER3

Deep Standby Interrupt Enable Register 3
address_offset : 0x405 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUSBFSIE : USBFS Suspend/Resume Deep Standby Cancel Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DAGT1IE : AGT1 Underflow Deep Standby Cancel Signal Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DPSIFR0

Deep Standby Interrupt Flag Register 0
address_offset : 0x406 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ0F : IRQ0-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ1F : IRQ1-DS Pin Deep Standby Cancel Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ4F : IRQ4-DS Pin Deep Standby Cancel Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ5F : IRQ5-DS Pin Deep Standby Cancel Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ6F : IRQ6-DS Pin Deep Standby Cancel Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ7F : IRQ7-DS Pin Deep Standby Cancel Flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DPSIFR1

Deep Standby Interrupt Flag Register 1
address_offset : 0x407 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ8F : IRQ8-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ9F : IRQ9-DS Pin Deep Standby Cancel Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ10F : IRQ10-DS Pin Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ11F : IRQ11-DS Pin Deep Standby Cancel Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ12F : IRQ12-DS Pin Deep Standby Cancel Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DPSIFR2

Deep Standby Interrupt Flag Register 2
address_offset : 0x408 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLVD1IF : LVD1 Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DLVD2IF : LVD2 Deep Standby Cancel Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DTRTCIIF : RTC Interval interrupt Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DRTCAIF : RTC Alarm interrupt Deep Standby Cancel Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DNMIF : NMI Pin Deep Standby Cancel Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DPSIFR3

Deep Standby Interrupt Flag Register 3
address_offset : 0x409 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUSBFSIF : USBFS Suspend/Resume Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DAGT1IF : AGT1 Underflow Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DPSIEGR0

Deep Standby Interrupt Edge Register 0
address_offset : 0x40A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ0EG : IRQ0-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ1EG : IRQ1-DS Pin Edge Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ4EG : IRQ4-DS Pin Edge Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ5EG : IRQ5-DS Pin Edge Select
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ6EG : IRQ6-DS Pin Edge Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ7EG : IRQ7-DS Pin Edge Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DPSIEGR1

Deep Standby Interrupt Edge Register 1
address_offset : 0x40B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ8EG : IRQ8-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ9EG : IRQ9-DS Pin Edge Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ10EG : IRQ10-DS Pin Edge Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ11EG : IRQ11-DS Pin Edge Select
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ12EG : IRQ12-DS Pin Edge Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DPSIEGR2

Deep Standby Interrupt Edge Register 2
address_offset : 0x40C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLVD1IEG : LVD1 Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated when VCC

#1 : 1

A cancel request is generated when VCC>=Vdet1 (rise) is detected

End of enumeration elements list.

DLVD2IEG : LVD2 Edge Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated when VCC

#1 : 1

A cancel request is generated when VCC>=Vdet2 (rise) is detected

End of enumeration elements list.

DNMIEG : NMI Pin Edge Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

SYOCDCR

System Control OCD Control Register
address_offset : 0x40E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOCDF : Deep Standby OCD flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

On-chip debugger is disabled

#1 : 1

On-chip debugger is enabled

End of enumeration elements list.

DBGEN : Debugger Enable bit
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

On-chip debugger is disabled

#1 : 1

On-chip debugger is enabled

End of enumeration elements list.

STCONR

Standby Condition Register
address_offset : 0x40F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCON : SSTBY condition bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

set this value in case of transferring to Software Standby Mode in using HOCO.

#11 : 11

set this value in case of transferring to Software Standby Mode in using expect for HOCO.

End of enumeration elements list.

OSTDSR

Oscillation Stop Detection Status Register
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTDF : Oscillation Stop Detection Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Main clock oscillation stop not detected

#1 : 1

Main clock oscillation stop detected

End of enumeration elements list.

RSTSR0

Reset Status Register 0
address_offset : 0x410 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORF : Power-On Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Power-on reset not detected.

#1 : 1

Power-on reset detected.

End of enumeration elements list.

LVD0RF : Voltage Monitor 0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor 0 reset not detected.

#1 : 1

Voltage Monitor 0 reset detected.

End of enumeration elements list.

LVD1RF : Voltage Monitor 1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor 1 reset not detected.

#1 : 1

Voltage Monitor 1 reset detected.

End of enumeration elements list.

LVD2RF : Voltage Monitor 2 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor 2 reset not detected.

#1 : 1

Voltage Monitor 2 reset detected.

End of enumeration elements list.

DPSRSTF : Deep Software Standby Reset FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Deep software standby mode cancelation not requested by an interrupt.

#1 : 1

Deep software standby mode cancelation requested by an interrupt.

End of enumeration elements list.

RSTSR2

Reset Status Register 2
address_offset : 0x411 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWSF : Cold/Warm Start Determination Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cold start

#1 : 1

Warm start

End of enumeration elements list.

MOMCR

Main Clock Oscillator Mode Oscillation Control Register
address_offset : 0x413 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODRV0 : Main Clock Oscillator Drive Capability 0 Switching
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

20MHz to 24MHz

#01 : 01

16MHz to 20MHz

#10 : 10

8MHz to 16MHz

#11 : 11

8MHz

End of enumeration elements list.

MOSEL : Main Clock Oscillator Switching
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Resonator

#1 : 1

External clock input

End of enumeration elements list.

AUTODRVEN : Main Clock Oscillator Drive Capability Auto Switching Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable.

End of enumeration elements list.

FWEPROR

Flash P/E Protect Register
address_offset : 0x416 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLWE : Flash Programming and Erasure
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Prohibits programming and erasure of the code flash, data flash or blank checking.

#01 : 01

Permits programming and erasure of the code flash, data flash or blank checking.

#10 : 10

Prohibits programming and erasure of the code flash, data flash or blank checking.

#11 : 11

Prohibits programming and erasure of the code flash, data flash or blank checking.

End of enumeration elements list.

LVCMPCR

Voltage Monitor Circuit Control Register
address_offset : 0x417 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1E : Voltage Detection 1 Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage detection 1 circuit disabled

#1 : 1

Voltage detection 1 circuit enabled

End of enumeration elements list.

LVD2E : Voltage Detection 2 Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage detection 2 circuit disabled

#1 : 1

Voltage detection 2 circuit enabled

End of enumeration elements list.

LVDLVLR

Voltage Detection Level Select Register
address_offset : 0x418 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1LVL : Voltage Detection 1 Level Select (Standard voltage during fall in voltage)
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#10001 : 10001

2.99V (Vdet1_1)

#10010 : 10010

2.92V (Vdet1_2)

#10011 : 10011

2.85V (Vdet1_3)

: others

Settings other than above are prohibited.

End of enumeration elements list.

LVD2LVL : Voltage Detection 2 Level Select (Standard voltage during fall in voltage)
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#101 : 101

2.99V (Vdet2_1)

#110 : 110

2.92V (Vdet2_2)

#111 : 111

2.85V (Vdet2_3)

: others

Settings other than above are prohibited.

End of enumeration elements list.

LVD1CR0

Voltage Monitor %s Circuit Control Register 0
address_offset : 0x41A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIE : Voltage Monitor Interrupt/Reset Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

DFDIS : Voltage Monitor Digital Filter Disable Mode Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable digital filter

#1 : 1

Disable digital filter

End of enumeration elements list.

CMPE : Voltage Monitor Circuit Comparison Result Output Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable voltage monitor 1 circuit comparison result output

#1 : 1

Enable voltage monitor 1 circuit comparison result output.

End of enumeration elements list.

FSAMP : Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

1/2 LOCO frequency

#01 : 01

1/4 LOCO frequency

#10 : 10

1/8 LOCO frequency

#11 : 11

1/16 LOCO frequency

End of enumeration elements list.

RI : Voltage Monitor Circuit Mode Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor interrupt during Vdet1 passage

#1 : 1

Voltage Monitor reset enabled when the voltage falls to and below Vdet1

End of enumeration elements list.

RN : Voltage Monitor Reset Negate Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negation follows a stabilization time (tLVD) after VCC > Vdet is detected.

#1 : 1

Negation follows a stabilization time (tLVD) after assertion of the LVD reset.

End of enumeration elements list.

LVD2CR0

Voltage Monitor %s Circuit Control Register 0
address_offset : 0x41B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIE : Voltage Monitor Interrupt/Reset Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

DFDIS : Voltage Monitor Digital Filter Disable Mode Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable digital filter

#1 : 1

Disable digital filter

End of enumeration elements list.

CMPE : Voltage Monitor Circuit Comparison Result Output Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable voltage monitor 1 circuit comparison result output

#1 : 1

Enable voltage monitor 1 circuit comparison result output.

End of enumeration elements list.

FSAMP : Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

1/2 LOCO frequency

#01 : 01

1/4 LOCO frequency

#10 : 10

1/8 LOCO frequency

#11 : 11

1/16 LOCO frequency

End of enumeration elements list.

RI : Voltage Monitor Circuit Mode Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor interrupt during Vdet1 passage

#1 : 1

Voltage Monitor reset enabled when the voltage falls to and below Vdet1

End of enumeration elements list.

RN : Voltage Monitor Reset Negate Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negation follows a stabilization time (tLVD) after VCC > Vdet is detected.

#1 : 1

Negation follows a stabilization time (tLVD) after assertion of the LVD reset.

End of enumeration elements list.

SOSCCR

Sub-clock oscillator control register
address_offset : 0x480 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOSTP : Sub-Clock Oscillator Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the sub-clock oscillator

#1 : 1

Stop the sub-clock oscillator

End of enumeration elements list.

SOMCR

Sub Clock Oscillator Mode Control Register
address_offset : 0x481 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SODRV1 : Sub Clock Oscillator Drive Capability Switching
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Standard

#1 : 1

Middle

End of enumeration elements list.

LOCOCR

Low-Speed On-Chip Oscillator Control Register
address_offset : 0x490 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCSTP : LOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the LOCO clock

#1 : 1

Stop the LOCO clock

End of enumeration elements list.

LOCOUTCR

LOCO User Trimming Control Register
address_offset : 0x492 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCOUTRM : LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO trimming bits
bits : 0 - 6 (7 bit)
access : read-write

VBTICTLR

VBATT Input Control Register
address_offset : 0x4BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCH0INEN : RTCIC0 Input Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

VCH1INEN : RTCIC1 Input Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

VCH2INEN : RTCIC2 Input Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

VBTBKR0

VBATT Backup Register [%s]
address_offset : 0x500 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR : VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset.
bits : 0 - 6 (7 bit)
access : read-write

VBTBKR1

VBATT Backup Register [%s]
address_offset : 0x501 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR2

VBATT Backup Register [%s]
address_offset : 0x502 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR3

VBATT Backup Register [%s]
address_offset : 0x503 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR4

VBATT Backup Register [%s]
address_offset : 0x504 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR5

VBATT Backup Register [%s]
address_offset : 0x505 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR6

VBATT Backup Register [%s]
address_offset : 0x506 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR7

VBATT Backup Register [%s]
address_offset : 0x507 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR8

VBATT Backup Register [%s]
address_offset : 0x508 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR9

VBATT Backup Register [%s]
address_offset : 0x509 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR10

VBATT Backup Register [%s]
address_offset : 0x50A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR11

VBATT Backup Register [%s]
address_offset : 0x50B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR12

VBATT Backup Register [%s]
address_offset : 0x50C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR13

VBATT Backup Register [%s]
address_offset : 0x50D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR14

VBATT Backup Register [%s]
address_offset : 0x50E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR15

VBATT Backup Register [%s]
address_offset : 0x50F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR16

VBATT Backup Register [%s]
address_offset : 0x510 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR17

VBATT Backup Register [%s]
address_offset : 0x511 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR18

VBATT Backup Register [%s]
address_offset : 0x512 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR19

VBATT Backup Register [%s]
address_offset : 0x513 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR20

VBATT Backup Register [%s]
address_offset : 0x514 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR21

VBATT Backup Register [%s]
address_offset : 0x515 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR22

VBATT Backup Register [%s]
address_offset : 0x516 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR23

VBATT Backup Register [%s]
address_offset : 0x517 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR24

VBATT Backup Register [%s]
address_offset : 0x518 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR25

VBATT Backup Register [%s]
address_offset : 0x519 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR26

VBATT Backup Register [%s]
address_offset : 0x51A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR27

VBATT Backup Register [%s]
address_offset : 0x51B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR28

VBATT Backup Register [%s]
address_offset : 0x51C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR29

VBATT Backup Register [%s]
address_offset : 0x51D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR30

VBATT Backup Register [%s]
address_offset : 0x51E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR31

VBATT Backup Register [%s]
address_offset : 0x51F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EBCKOCR

External Bus Clock Output Control Register
address_offset : 0x52 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EBCKOEN : BCLK Pin Output Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable EBCLK pin output (fixed high)

#1 : 1

Enable EBCLK pin output

End of enumeration elements list.

VBTBKR32

VBATT Backup Register [%s]
address_offset : 0x520 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR33

VBATT Backup Register [%s]
address_offset : 0x521 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR34

VBATT Backup Register [%s]
address_offset : 0x522 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR35

VBATT Backup Register [%s]
address_offset : 0x523 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR36

VBATT Backup Register [%s]
address_offset : 0x524 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR37

VBATT Backup Register [%s]
address_offset : 0x525 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR38

VBATT Backup Register [%s]
address_offset : 0x526 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR39

VBATT Backup Register [%s]
address_offset : 0x527 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR40

VBATT Backup Register [%s]
address_offset : 0x528 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR41

VBATT Backup Register [%s]
address_offset : 0x529 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR42

VBATT Backup Register [%s]
address_offset : 0x52A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR43

VBATT Backup Register [%s]
address_offset : 0x52B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR44

VBATT Backup Register [%s]
address_offset : 0x52C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR45

VBATT Backup Register [%s]
address_offset : 0x52D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR46

VBATT Backup Register [%s]
address_offset : 0x52E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR47

VBATT Backup Register [%s]
address_offset : 0x52F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCKOCR

SDRAM Clock Output Control Register
address_offset : 0x53 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCKOEN : SDCLK Pin Output Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SDCLK pin output (fixed high)

#1 : 1

Enable SDCLK pin output

End of enumeration elements list.

VBTBKR48

VBATT Backup Register [%s]
address_offset : 0x530 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR49

VBATT Backup Register [%s]
address_offset : 0x531 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR50

VBATT Backup Register [%s]
address_offset : 0x532 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR51

VBATT Backup Register [%s]
address_offset : 0x533 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR52

VBATT Backup Register [%s]
address_offset : 0x534 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR53

VBATT Backup Register [%s]
address_offset : 0x535 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR54

VBATT Backup Register [%s]
address_offset : 0x536 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR55

VBATT Backup Register [%s]
address_offset : 0x537 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR56

VBATT Backup Register [%s]
address_offset : 0x538 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR57

VBATT Backup Register [%s]
address_offset : 0x539 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR58

VBATT Backup Register [%s]
address_offset : 0x53A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR59

VBATT Backup Register [%s]
address_offset : 0x53B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR60

VBATT Backup Register [%s]
address_offset : 0x53C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR61

VBATT Backup Register [%s]
address_offset : 0x53D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR62

VBATT Backup Register [%s]
address_offset : 0x53E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR63

VBATT Backup Register [%s]
address_offset : 0x53F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR64

VBATT Backup Register [%s]
address_offset : 0x540 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR65

VBATT Backup Register [%s]
address_offset : 0x541 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR66

VBATT Backup Register [%s]
address_offset : 0x542 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR67

VBATT Backup Register [%s]
address_offset : 0x543 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR68

VBATT Backup Register [%s]
address_offset : 0x544 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR69

VBATT Backup Register [%s]
address_offset : 0x545 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR70

VBATT Backup Register [%s]
address_offset : 0x546 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR71

VBATT Backup Register [%s]
address_offset : 0x547 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR72

VBATT Backup Register [%s]
address_offset : 0x548 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR73

VBATT Backup Register [%s]
address_offset : 0x549 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR74

VBATT Backup Register [%s]
address_offset : 0x54A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR75

VBATT Backup Register [%s]
address_offset : 0x54B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR76

VBATT Backup Register [%s]
address_offset : 0x54C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR77

VBATT Backup Register [%s]
address_offset : 0x54D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR78

VBATT Backup Register [%s]
address_offset : 0x54E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR79

VBATT Backup Register [%s]
address_offset : 0x54F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR80

VBATT Backup Register [%s]
address_offset : 0x550 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR81

VBATT Backup Register [%s]
address_offset : 0x551 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR82

VBATT Backup Register [%s]
address_offset : 0x552 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR83

VBATT Backup Register [%s]
address_offset : 0x553 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR84

VBATT Backup Register [%s]
address_offset : 0x554 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR85

VBATT Backup Register [%s]
address_offset : 0x555 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR86

VBATT Backup Register [%s]
address_offset : 0x556 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR87

VBATT Backup Register [%s]
address_offset : 0x557 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR88

VBATT Backup Register [%s]
address_offset : 0x558 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR89

VBATT Backup Register [%s]
address_offset : 0x559 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR90

VBATT Backup Register [%s]
address_offset : 0x55A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR91

VBATT Backup Register [%s]
address_offset : 0x55B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR92

VBATT Backup Register [%s]
address_offset : 0x55C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR93

VBATT Backup Register [%s]
address_offset : 0x55D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR94

VBATT Backup Register [%s]
address_offset : 0x55E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR95

VBATT Backup Register [%s]
address_offset : 0x55F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR96

VBATT Backup Register [%s]
address_offset : 0x560 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR97

VBATT Backup Register [%s]
address_offset : 0x561 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR98

VBATT Backup Register [%s]
address_offset : 0x562 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR99

VBATT Backup Register [%s]
address_offset : 0x563 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR100

VBATT Backup Register [%s]
address_offset : 0x564 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR101

VBATT Backup Register [%s]
address_offset : 0x565 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR102

VBATT Backup Register [%s]
address_offset : 0x566 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR103

VBATT Backup Register [%s]
address_offset : 0x567 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR104

VBATT Backup Register [%s]
address_offset : 0x568 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR105

VBATT Backup Register [%s]
address_offset : 0x569 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR106

VBATT Backup Register [%s]
address_offset : 0x56A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR107

VBATT Backup Register [%s]
address_offset : 0x56B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR108

VBATT Backup Register [%s]
address_offset : 0x56C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR109

VBATT Backup Register [%s]
address_offset : 0x56D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR110

VBATT Backup Register [%s]
address_offset : 0x56E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR111

VBATT Backup Register [%s]
address_offset : 0x56F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR112

VBATT Backup Register [%s]
address_offset : 0x570 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR113

VBATT Backup Register [%s]
address_offset : 0x571 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR114

VBATT Backup Register [%s]
address_offset : 0x572 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR115

VBATT Backup Register [%s]
address_offset : 0x573 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR116

VBATT Backup Register [%s]
address_offset : 0x574 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR117

VBATT Backup Register [%s]
address_offset : 0x575 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR118

VBATT Backup Register [%s]
address_offset : 0x576 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR119

VBATT Backup Register [%s]
address_offset : 0x577 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR120

VBATT Backup Register [%s]
address_offset : 0x578 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR121

VBATT Backup Register [%s]
address_offset : 0x579 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR122

VBATT Backup Register [%s]
address_offset : 0x57A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR123

VBATT Backup Register [%s]
address_offset : 0x57B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR124

VBATT Backup Register [%s]
address_offset : 0x57C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR125

VBATT Backup Register [%s]
address_offset : 0x57D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR126

VBATT Backup Register [%s]
address_offset : 0x57E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR127

VBATT Backup Register [%s]
address_offset : 0x57F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR128

VBATT Backup Register [%s]
address_offset : 0x580 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR129

VBATT Backup Register [%s]
address_offset : 0x581 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR130

VBATT Backup Register [%s]
address_offset : 0x582 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR131

VBATT Backup Register [%s]
address_offset : 0x583 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR132

VBATT Backup Register [%s]
address_offset : 0x584 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR133

VBATT Backup Register [%s]
address_offset : 0x585 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR134

VBATT Backup Register [%s]
address_offset : 0x586 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR135

VBATT Backup Register [%s]
address_offset : 0x587 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR136

VBATT Backup Register [%s]
address_offset : 0x588 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR137

VBATT Backup Register [%s]
address_offset : 0x589 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR138

VBATT Backup Register [%s]
address_offset : 0x58A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR139

VBATT Backup Register [%s]
address_offset : 0x58B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR140

VBATT Backup Register [%s]
address_offset : 0x58C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR141

VBATT Backup Register [%s]
address_offset : 0x58D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR142

VBATT Backup Register [%s]
address_offset : 0x58E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR143

VBATT Backup Register [%s]
address_offset : 0x58F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR144

VBATT Backup Register [%s]
address_offset : 0x590 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR145

VBATT Backup Register [%s]
address_offset : 0x591 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR146

VBATT Backup Register [%s]
address_offset : 0x592 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR147

VBATT Backup Register [%s]
address_offset : 0x593 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR148

VBATT Backup Register [%s]
address_offset : 0x594 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR149

VBATT Backup Register [%s]
address_offset : 0x595 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR150

VBATT Backup Register [%s]
address_offset : 0x596 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR151

VBATT Backup Register [%s]
address_offset : 0x597 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR152

VBATT Backup Register [%s]
address_offset : 0x598 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR153

VBATT Backup Register [%s]
address_offset : 0x599 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR154

VBATT Backup Register [%s]
address_offset : 0x59A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR155

VBATT Backup Register [%s]
address_offset : 0x59B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR156

VBATT Backup Register [%s]
address_offset : 0x59C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR157

VBATT Backup Register [%s]
address_offset : 0x59D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR158

VBATT Backup Register [%s]
address_offset : 0x59E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR159

VBATT Backup Register [%s]
address_offset : 0x59F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR160

VBATT Backup Register [%s]
address_offset : 0x5A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR161

VBATT Backup Register [%s]
address_offset : 0x5A1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR162

VBATT Backup Register [%s]
address_offset : 0x5A2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR163

VBATT Backup Register [%s]
address_offset : 0x5A3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR164

VBATT Backup Register [%s]
address_offset : 0x5A4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR165

VBATT Backup Register [%s]
address_offset : 0x5A5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR166

VBATT Backup Register [%s]
address_offset : 0x5A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR167

VBATT Backup Register [%s]
address_offset : 0x5A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR168

VBATT Backup Register [%s]
address_offset : 0x5A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR169

VBATT Backup Register [%s]
address_offset : 0x5A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR170

VBATT Backup Register [%s]
address_offset : 0x5AA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR171

VBATT Backup Register [%s]
address_offset : 0x5AB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR172

VBATT Backup Register [%s]
address_offset : 0x5AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR173

VBATT Backup Register [%s]
address_offset : 0x5AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR174

VBATT Backup Register [%s]
address_offset : 0x5AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR175

VBATT Backup Register [%s]
address_offset : 0x5AF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR176

VBATT Backup Register [%s]
address_offset : 0x5B0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR177

VBATT Backup Register [%s]
address_offset : 0x5B1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR178

VBATT Backup Register [%s]
address_offset : 0x5B2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR179

VBATT Backup Register [%s]
address_offset : 0x5B3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR180

VBATT Backup Register [%s]
address_offset : 0x5B4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR181

VBATT Backup Register [%s]
address_offset : 0x5B5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR182

VBATT Backup Register [%s]
address_offset : 0x5B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR183

VBATT Backup Register [%s]
address_offset : 0x5B7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR184

VBATT Backup Register [%s]
address_offset : 0x5B8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR185

VBATT Backup Register [%s]
address_offset : 0x5B9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR186

VBATT Backup Register [%s]
address_offset : 0x5BA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR187

VBATT Backup Register [%s]
address_offset : 0x5BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR188

VBATT Backup Register [%s]
address_offset : 0x5BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR189

VBATT Backup Register [%s]
address_offset : 0x5BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR190

VBATT Backup Register [%s]
address_offset : 0x5BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR191

VBATT Backup Register [%s]
address_offset : 0x5BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR192

VBATT Backup Register [%s]
address_offset : 0x5C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR193

VBATT Backup Register [%s]
address_offset : 0x5C1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR194

VBATT Backup Register [%s]
address_offset : 0x5C2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR195

VBATT Backup Register [%s]
address_offset : 0x5C3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR196

VBATT Backup Register [%s]
address_offset : 0x5C4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR197

VBATT Backup Register [%s]
address_offset : 0x5C5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR198

VBATT Backup Register [%s]
address_offset : 0x5C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR199

VBATT Backup Register [%s]
address_offset : 0x5C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR200

VBATT Backup Register [%s]
address_offset : 0x5C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR201

VBATT Backup Register [%s]
address_offset : 0x5C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR202

VBATT Backup Register [%s]
address_offset : 0x5CA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR203

VBATT Backup Register [%s]
address_offset : 0x5CB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR204

VBATT Backup Register [%s]
address_offset : 0x5CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR205

VBATT Backup Register [%s]
address_offset : 0x5CD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR206

VBATT Backup Register [%s]
address_offset : 0x5CE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR207

VBATT Backup Register [%s]
address_offset : 0x5CF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR208

VBATT Backup Register [%s]
address_offset : 0x5D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR209

VBATT Backup Register [%s]
address_offset : 0x5D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR210

VBATT Backup Register [%s]
address_offset : 0x5D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR211

VBATT Backup Register [%s]
address_offset : 0x5D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR212

VBATT Backup Register [%s]
address_offset : 0x5D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR213

VBATT Backup Register [%s]
address_offset : 0x5D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR214

VBATT Backup Register [%s]
address_offset : 0x5D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR215

VBATT Backup Register [%s]
address_offset : 0x5D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR216

VBATT Backup Register [%s]
address_offset : 0x5D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR217

VBATT Backup Register [%s]
address_offset : 0x5D9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR218

VBATT Backup Register [%s]
address_offset : 0x5DA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR219

VBATT Backup Register [%s]
address_offset : 0x5DB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR220

VBATT Backup Register [%s]
address_offset : 0x5DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR221

VBATT Backup Register [%s]
address_offset : 0x5DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR222

VBATT Backup Register [%s]
address_offset : 0x5DE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR223

VBATT Backup Register [%s]
address_offset : 0x5DF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR224

VBATT Backup Register [%s]
address_offset : 0x5E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR225

VBATT Backup Register [%s]
address_offset : 0x5E1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR226

VBATT Backup Register [%s]
address_offset : 0x5E2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR227

VBATT Backup Register [%s]
address_offset : 0x5E3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR228

VBATT Backup Register [%s]
address_offset : 0x5E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR229

VBATT Backup Register [%s]
address_offset : 0x5E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR230

VBATT Backup Register [%s]
address_offset : 0x5E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR231

VBATT Backup Register [%s]
address_offset : 0x5E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR232

VBATT Backup Register [%s]
address_offset : 0x5E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR233

VBATT Backup Register [%s]
address_offset : 0x5E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR234

VBATT Backup Register [%s]
address_offset : 0x5EA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR235

VBATT Backup Register [%s]
address_offset : 0x5EB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR236

VBATT Backup Register [%s]
address_offset : 0x5EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR237

VBATT Backup Register [%s]
address_offset : 0x5ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR238

VBATT Backup Register [%s]
address_offset : 0x5EE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR239

VBATT Backup Register [%s]
address_offset : 0x5EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR240

VBATT Backup Register [%s]
address_offset : 0x5F0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR241

VBATT Backup Register [%s]
address_offset : 0x5F1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR242

VBATT Backup Register [%s]
address_offset : 0x5F2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR243

VBATT Backup Register [%s]
address_offset : 0x5F3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR244

VBATT Backup Register [%s]
address_offset : 0x5F4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR245

VBATT Backup Register [%s]
address_offset : 0x5F5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR246

VBATT Backup Register [%s]
address_offset : 0x5F6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR247

VBATT Backup Register [%s]
address_offset : 0x5F7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR248

VBATT Backup Register [%s]
address_offset : 0x5F8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR249

VBATT Backup Register [%s]
address_offset : 0x5F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR250

VBATT Backup Register [%s]
address_offset : 0x5FA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR251

VBATT Backup Register [%s]
address_offset : 0x5FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR252

VBATT Backup Register [%s]
address_offset : 0x5FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR253

VBATT Backup Register [%s]
address_offset : 0x5FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR254

VBATT Backup Register [%s]
address_offset : 0x5FE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR255

VBATT Backup Register [%s]
address_offset : 0x5FF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR256

VBATT Backup Register [%s]
address_offset : 0x600 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR257

VBATT Backup Register [%s]
address_offset : 0x601 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR258

VBATT Backup Register [%s]
address_offset : 0x602 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR259

VBATT Backup Register [%s]
address_offset : 0x603 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR260

VBATT Backup Register [%s]
address_offset : 0x604 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR261

VBATT Backup Register [%s]
address_offset : 0x605 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR262

VBATT Backup Register [%s]
address_offset : 0x606 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR263

VBATT Backup Register [%s]
address_offset : 0x607 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR264

VBATT Backup Register [%s]
address_offset : 0x608 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR265

VBATT Backup Register [%s]
address_offset : 0x609 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR266

VBATT Backup Register [%s]
address_offset : 0x60A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR267

VBATT Backup Register [%s]
address_offset : 0x60B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR268

VBATT Backup Register [%s]
address_offset : 0x60C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR269

VBATT Backup Register [%s]
address_offset : 0x60D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR270

VBATT Backup Register [%s]
address_offset : 0x60E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR271

VBATT Backup Register [%s]
address_offset : 0x60F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOCOUTCR

MOCO User Trimming Control Register
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOCOUTRM : MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO trimming bits
bits : 0 - 6 (7 bit)
access : read-write

VBTBKR272

VBATT Backup Register [%s]
address_offset : 0x610 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR273

VBATT Backup Register [%s]
address_offset : 0x611 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR274

VBATT Backup Register [%s]
address_offset : 0x612 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR275

VBATT Backup Register [%s]
address_offset : 0x613 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR276

VBATT Backup Register [%s]
address_offset : 0x614 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR277

VBATT Backup Register [%s]
address_offset : 0x615 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR278

VBATT Backup Register [%s]
address_offset : 0x616 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR279

VBATT Backup Register [%s]
address_offset : 0x617 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR280

VBATT Backup Register [%s]
address_offset : 0x618 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR281

VBATT Backup Register [%s]
address_offset : 0x619 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR282

VBATT Backup Register [%s]
address_offset : 0x61A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR283

VBATT Backup Register [%s]
address_offset : 0x61B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR284

VBATT Backup Register [%s]
address_offset : 0x61C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR285

VBATT Backup Register [%s]
address_offset : 0x61D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR286

VBATT Backup Register [%s]
address_offset : 0x61E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR287

VBATT Backup Register [%s]
address_offset : 0x61F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCOUTCR

HOCO User Trimming Control Register
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCOUTRM : HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO trimming bits
bits : 0 - 6 (7 bit)
access : read-write

VBTBKR288

VBATT Backup Register [%s]
address_offset : 0x620 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR289

VBATT Backup Register [%s]
address_offset : 0x621 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR290

VBATT Backup Register [%s]
address_offset : 0x622 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR291

VBATT Backup Register [%s]
address_offset : 0x623 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR292

VBATT Backup Register [%s]
address_offset : 0x624 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR293

VBATT Backup Register [%s]
address_offset : 0x625 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR294

VBATT Backup Register [%s]
address_offset : 0x626 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR295

VBATT Backup Register [%s]
address_offset : 0x627 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR296

VBATT Backup Register [%s]
address_offset : 0x628 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR297

VBATT Backup Register [%s]
address_offset : 0x629 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR298

VBATT Backup Register [%s]
address_offset : 0x62A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR299

VBATT Backup Register [%s]
address_offset : 0x62B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR300

VBATT Backup Register [%s]
address_offset : 0x62C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR301

VBATT Backup Register [%s]
address_offset : 0x62D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR302

VBATT Backup Register [%s]
address_offset : 0x62E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR303

VBATT Backup Register [%s]
address_offset : 0x62F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR304

VBATT Backup Register [%s]
address_offset : 0x630 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR305

VBATT Backup Register [%s]
address_offset : 0x631 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR306

VBATT Backup Register [%s]
address_offset : 0x632 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR307

VBATT Backup Register [%s]
address_offset : 0x633 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR308

VBATT Backup Register [%s]
address_offset : 0x634 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR309

VBATT Backup Register [%s]
address_offset : 0x635 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR310

VBATT Backup Register [%s]
address_offset : 0x636 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR311

VBATT Backup Register [%s]
address_offset : 0x637 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR312

VBATT Backup Register [%s]
address_offset : 0x638 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR313

VBATT Backup Register [%s]
address_offset : 0x639 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR314

VBATT Backup Register [%s]
address_offset : 0x63A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR315

VBATT Backup Register [%s]
address_offset : 0x63B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR316

VBATT Backup Register [%s]
address_offset : 0x63C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR317

VBATT Backup Register [%s]
address_offset : 0x63D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR318

VBATT Backup Register [%s]
address_offset : 0x63E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR319

VBATT Backup Register [%s]
address_offset : 0x63F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR320

VBATT Backup Register [%s]
address_offset : 0x640 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR321

VBATT Backup Register [%s]
address_offset : 0x641 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR322

VBATT Backup Register [%s]
address_offset : 0x642 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR323

VBATT Backup Register [%s]
address_offset : 0x643 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR324

VBATT Backup Register [%s]
address_offset : 0x644 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR325

VBATT Backup Register [%s]
address_offset : 0x645 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR326

VBATT Backup Register [%s]
address_offset : 0x646 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR327

VBATT Backup Register [%s]
address_offset : 0x647 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR328

VBATT Backup Register [%s]
address_offset : 0x648 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR329

VBATT Backup Register [%s]
address_offset : 0x649 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR330

VBATT Backup Register [%s]
address_offset : 0x64A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR331

VBATT Backup Register [%s]
address_offset : 0x64B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR332

VBATT Backup Register [%s]
address_offset : 0x64C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR333

VBATT Backup Register [%s]
address_offset : 0x64D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR334

VBATT Backup Register [%s]
address_offset : 0x64E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR335

VBATT Backup Register [%s]
address_offset : 0x64F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR336

VBATT Backup Register [%s]
address_offset : 0x650 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR337

VBATT Backup Register [%s]
address_offset : 0x651 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR338

VBATT Backup Register [%s]
address_offset : 0x652 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR339

VBATT Backup Register [%s]
address_offset : 0x653 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR340

VBATT Backup Register [%s]
address_offset : 0x654 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR341

VBATT Backup Register [%s]
address_offset : 0x655 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR342

VBATT Backup Register [%s]
address_offset : 0x656 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR343

VBATT Backup Register [%s]
address_offset : 0x657 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR344

VBATT Backup Register [%s]
address_offset : 0x658 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR345

VBATT Backup Register [%s]
address_offset : 0x659 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR346

VBATT Backup Register [%s]
address_offset : 0x65A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR347

VBATT Backup Register [%s]
address_offset : 0x65B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR348

VBATT Backup Register [%s]
address_offset : 0x65C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR349

VBATT Backup Register [%s]
address_offset : 0x65D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR350

VBATT Backup Register [%s]
address_offset : 0x65E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR351

VBATT Backup Register [%s]
address_offset : 0x65F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR352

VBATT Backup Register [%s]
address_offset : 0x660 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR353

VBATT Backup Register [%s]
address_offset : 0x661 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR354

VBATT Backup Register [%s]
address_offset : 0x662 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR355

VBATT Backup Register [%s]
address_offset : 0x663 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR356

VBATT Backup Register [%s]
address_offset : 0x664 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR357

VBATT Backup Register [%s]
address_offset : 0x665 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR358

VBATT Backup Register [%s]
address_offset : 0x666 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR359

VBATT Backup Register [%s]
address_offset : 0x667 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR360

VBATT Backup Register [%s]
address_offset : 0x668 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR361

VBATT Backup Register [%s]
address_offset : 0x669 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR362

VBATT Backup Register [%s]
address_offset : 0x66A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR363

VBATT Backup Register [%s]
address_offset : 0x66B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR364

VBATT Backup Register [%s]
address_offset : 0x66C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR365

VBATT Backup Register [%s]
address_offset : 0x66D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR366

VBATT Backup Register [%s]
address_offset : 0x66E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR367

VBATT Backup Register [%s]
address_offset : 0x66F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR368

VBATT Backup Register [%s]
address_offset : 0x670 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR369

VBATT Backup Register [%s]
address_offset : 0x671 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR370

VBATT Backup Register [%s]
address_offset : 0x672 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR371

VBATT Backup Register [%s]
address_offset : 0x673 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR372

VBATT Backup Register [%s]
address_offset : 0x674 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR373

VBATT Backup Register [%s]
address_offset : 0x675 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR374

VBATT Backup Register [%s]
address_offset : 0x676 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR375

VBATT Backup Register [%s]
address_offset : 0x677 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR376

VBATT Backup Register [%s]
address_offset : 0x678 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR377

VBATT Backup Register [%s]
address_offset : 0x679 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR378

VBATT Backup Register [%s]
address_offset : 0x67A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR379

VBATT Backup Register [%s]
address_offset : 0x67B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR380

VBATT Backup Register [%s]
address_offset : 0x67C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR381

VBATT Backup Register [%s]
address_offset : 0x67D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR382

VBATT Backup Register [%s]
address_offset : 0x67E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR383

VBATT Backup Register [%s]
address_offset : 0x67F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR384

VBATT Backup Register [%s]
address_offset : 0x680 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR385

VBATT Backup Register [%s]
address_offset : 0x681 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR386

VBATT Backup Register [%s]
address_offset : 0x682 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR387

VBATT Backup Register [%s]
address_offset : 0x683 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR388

VBATT Backup Register [%s]
address_offset : 0x684 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR389

VBATT Backup Register [%s]
address_offset : 0x685 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR390

VBATT Backup Register [%s]
address_offset : 0x686 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR391

VBATT Backup Register [%s]
address_offset : 0x687 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR392

VBATT Backup Register [%s]
address_offset : 0x688 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR393

VBATT Backup Register [%s]
address_offset : 0x689 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR394

VBATT Backup Register [%s]
address_offset : 0x68A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR395

VBATT Backup Register [%s]
address_offset : 0x68B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR396

VBATT Backup Register [%s]
address_offset : 0x68C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR397

VBATT Backup Register [%s]
address_offset : 0x68D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR398

VBATT Backup Register [%s]
address_offset : 0x68E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR399

VBATT Backup Register [%s]
address_offset : 0x68F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR400

VBATT Backup Register [%s]
address_offset : 0x690 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR401

VBATT Backup Register [%s]
address_offset : 0x691 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR402

VBATT Backup Register [%s]
address_offset : 0x692 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR403

VBATT Backup Register [%s]
address_offset : 0x693 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR404

VBATT Backup Register [%s]
address_offset : 0x694 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR405

VBATT Backup Register [%s]
address_offset : 0x695 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR406

VBATT Backup Register [%s]
address_offset : 0x696 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR407

VBATT Backup Register [%s]
address_offset : 0x697 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR408

VBATT Backup Register [%s]
address_offset : 0x698 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR409

VBATT Backup Register [%s]
address_offset : 0x699 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR410

VBATT Backup Register [%s]
address_offset : 0x69A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR411

VBATT Backup Register [%s]
address_offset : 0x69B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR412

VBATT Backup Register [%s]
address_offset : 0x69C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR413

VBATT Backup Register [%s]
address_offset : 0x69D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR414

VBATT Backup Register [%s]
address_offset : 0x69E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR415

VBATT Backup Register [%s]
address_offset : 0x69F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR416

VBATT Backup Register [%s]
address_offset : 0x6A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR417

VBATT Backup Register [%s]
address_offset : 0x6A1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR418

VBATT Backup Register [%s]
address_offset : 0x6A2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR419

VBATT Backup Register [%s]
address_offset : 0x6A3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR420

VBATT Backup Register [%s]
address_offset : 0x6A4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR421

VBATT Backup Register [%s]
address_offset : 0x6A5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR422

VBATT Backup Register [%s]
address_offset : 0x6A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR423

VBATT Backup Register [%s]
address_offset : 0x6A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR424

VBATT Backup Register [%s]
address_offset : 0x6A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR425

VBATT Backup Register [%s]
address_offset : 0x6A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR426

VBATT Backup Register [%s]
address_offset : 0x6AA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR427

VBATT Backup Register [%s]
address_offset : 0x6AB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR428

VBATT Backup Register [%s]
address_offset : 0x6AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR429

VBATT Backup Register [%s]
address_offset : 0x6AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR430

VBATT Backup Register [%s]
address_offset : 0x6AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR431

VBATT Backup Register [%s]
address_offset : 0x6AF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR432

VBATT Backup Register [%s]
address_offset : 0x6B0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR433

VBATT Backup Register [%s]
address_offset : 0x6B1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR434

VBATT Backup Register [%s]
address_offset : 0x6B2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR435

VBATT Backup Register [%s]
address_offset : 0x6B3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR436

VBATT Backup Register [%s]
address_offset : 0x6B4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR437

VBATT Backup Register [%s]
address_offset : 0x6B5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR438

VBATT Backup Register [%s]
address_offset : 0x6B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR439

VBATT Backup Register [%s]
address_offset : 0x6B7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR440

VBATT Backup Register [%s]
address_offset : 0x6B8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR441

VBATT Backup Register [%s]
address_offset : 0x6B9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR442

VBATT Backup Register [%s]
address_offset : 0x6BA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR443

VBATT Backup Register [%s]
address_offset : 0x6BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR444

VBATT Backup Register [%s]
address_offset : 0x6BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR445

VBATT Backup Register [%s]
address_offset : 0x6BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR446

VBATT Backup Register [%s]
address_offset : 0x6BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR447

VBATT Backup Register [%s]
address_offset : 0x6BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR448

VBATT Backup Register [%s]
address_offset : 0x6C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR449

VBATT Backup Register [%s]
address_offset : 0x6C1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR450

VBATT Backup Register [%s]
address_offset : 0x6C2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR451

VBATT Backup Register [%s]
address_offset : 0x6C3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR452

VBATT Backup Register [%s]
address_offset : 0x6C4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR453

VBATT Backup Register [%s]
address_offset : 0x6C5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR454

VBATT Backup Register [%s]
address_offset : 0x6C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR455

VBATT Backup Register [%s]
address_offset : 0x6C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR456

VBATT Backup Register [%s]
address_offset : 0x6C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR457

VBATT Backup Register [%s]
address_offset : 0x6C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR458

VBATT Backup Register [%s]
address_offset : 0x6CA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR459

VBATT Backup Register [%s]
address_offset : 0x6CB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR460

VBATT Backup Register [%s]
address_offset : 0x6CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR461

VBATT Backup Register [%s]
address_offset : 0x6CD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR462

VBATT Backup Register [%s]
address_offset : 0x6CE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR463

VBATT Backup Register [%s]
address_offset : 0x6CF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR464

VBATT Backup Register [%s]
address_offset : 0x6D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR465

VBATT Backup Register [%s]
address_offset : 0x6D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR466

VBATT Backup Register [%s]
address_offset : 0x6D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR467

VBATT Backup Register [%s]
address_offset : 0x6D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR468

VBATT Backup Register [%s]
address_offset : 0x6D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR469

VBATT Backup Register [%s]
address_offset : 0x6D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR470

VBATT Backup Register [%s]
address_offset : 0x6D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR471

VBATT Backup Register [%s]
address_offset : 0x6D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR472

VBATT Backup Register [%s]
address_offset : 0x6D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR473

VBATT Backup Register [%s]
address_offset : 0x6D9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR474

VBATT Backup Register [%s]
address_offset : 0x6DA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR475

VBATT Backup Register [%s]
address_offset : 0x6DB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR476

VBATT Backup Register [%s]
address_offset : 0x6DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR477

VBATT Backup Register [%s]
address_offset : 0x6DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR478

VBATT Backup Register [%s]
address_offset : 0x6DE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR479

VBATT Backup Register [%s]
address_offset : 0x6DF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR480

VBATT Backup Register [%s]
address_offset : 0x6E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR481

VBATT Backup Register [%s]
address_offset : 0x6E1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR482

VBATT Backup Register [%s]
address_offset : 0x6E2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR483

VBATT Backup Register [%s]
address_offset : 0x6E3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR484

VBATT Backup Register [%s]
address_offset : 0x6E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR485

VBATT Backup Register [%s]
address_offset : 0x6E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR486

VBATT Backup Register [%s]
address_offset : 0x6E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR487

VBATT Backup Register [%s]
address_offset : 0x6E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR488

VBATT Backup Register [%s]
address_offset : 0x6E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR489

VBATT Backup Register [%s]
address_offset : 0x6E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR490

VBATT Backup Register [%s]
address_offset : 0x6EA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR491

VBATT Backup Register [%s]
address_offset : 0x6EB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR492

VBATT Backup Register [%s]
address_offset : 0x6EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR493

VBATT Backup Register [%s]
address_offset : 0x6ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR494

VBATT Backup Register [%s]
address_offset : 0x6EE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR495

VBATT Backup Register [%s]
address_offset : 0x6EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR496

VBATT Backup Register [%s]
address_offset : 0x6F0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR497

VBATT Backup Register [%s]
address_offset : 0x6F1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR498

VBATT Backup Register [%s]
address_offset : 0x6F2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR499

VBATT Backup Register [%s]
address_offset : 0x6F3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR500

VBATT Backup Register [%s]
address_offset : 0x6F4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR501

VBATT Backup Register [%s]
address_offset : 0x6F5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR502

VBATT Backup Register [%s]
address_offset : 0x6F6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR503

VBATT Backup Register [%s]
address_offset : 0x6F7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR504

VBATT Backup Register [%s]
address_offset : 0x6F8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR505

VBATT Backup Register [%s]
address_offset : 0x6F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR506

VBATT Backup Register [%s]
address_offset : 0x6FA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR507

VBATT Backup Register [%s]
address_offset : 0x6FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR508

VBATT Backup Register [%s]
address_offset : 0x6FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR509

VBATT Backup Register [%s]
address_offset : 0x6FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR510

VBATT Backup Register [%s]
address_offset : 0x6FE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR511

VBATT Backup Register [%s]
address_offset : 0x6FF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZCR

Snooze Control Register
address_offset : 0x92 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXDREQEN : RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Ignore RXD0 falling edge in Standby mode.

#1 : 1

Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode.

End of enumeration elements list.

SNZDTCEN : DTC Enable in Snooze Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable DTC operation

#1 : 1

Enable DTC operation

End of enumeration elements list.

SNZE : Snooze Mode Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable Snooze Mode

#1 : 1

Enable Snooze Mode

End of enumeration elements list.

SNZEDCR

Snooze End Control Register
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGT1UNFED : AGT1 underflow Snooze End Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

DTCZRED : Last DTC transmission completion Snooze End Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

DTCNZRED : Not Last DTC transmission completion Snooze End Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

AD0MATED : AD compare match 0 Snooze End Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

AD0UMTED : AD compare mismatch 0 Snooze End Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

AD1MATED : AD compare match 1 Snooze End Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

AD1UMTED : AD compare mismatch 1 Snooze End Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

SCI0UMTED : SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode.
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

SNZREQCR

Snooze Request Control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZREQEN0 : Enable IRQ0 pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN1 : Enable IRQ1 pin snooze request
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN2 : Enable IRQ2 pin snooze request
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN3 : Enable IRQ3 pin snooze request
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN4 : Enable IRQ4 pin snooze request
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN5 : Enable IRQ5 pin snooze request
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN6 : Enable IRQ6 pin snooze request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN7 : Enable IRQ7 pin snooze request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN8 : Enable IRQ8 pin snooze request
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN9 : Enable IRQ9 pin snooze request
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN10 : Enable IRQ10 pin snooze request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN11 : Enable IRQ11 pin snooze request
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN12 : Enable IRQ12 pin snooze request
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN13 : Enable IRQ13 pin snooze request
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN17 : Enable KR snooze request
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN22 : Enable ACMPHS0 snooze request
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN24 : Enable RTC alarm snooze request
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN25 : Enable RTC period snooze request
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN28 : Enable AGT1 underflow snooze request
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN29 : Enable AGT1 compare match A snooze request
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN30 : Enable AGT1 compare match B snooze request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

OPCCR

Operating Power Control Register
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPCM : Operating Power Control Mode Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

High-speed mode

#01 : 01

Prohibited

#10 : 10

Prohibited

#11 : 11

Low-speed mode

: others

Setting prohibited

End of enumeration elements list.

OPCMTSF : Operating Power Control Mode Transition Status Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transition completed

#1 : 1

During transition

End of enumeration elements list.

MOSCWTCR

Main Clock Oscillator Wait Control Register
address_offset : 0xA2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSTS : Main clock oscillator wait time setting
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0001 : 0001

Wait time = 35 cycles (133.5 μs)

#0010 : 0010

Wait time = 67 cycles (255.6 μs)

#0011 : 0011

Wait time = 131 cycles (499.7 μs)

#0100 : 0100

Wait time = 259 cycles (988.0 μs)

#0101 : 0101

Wait time = 547 cycles (2086.6 μs) (value after reset)

#0110 : 0110

Wait time = 1059 cycles (4039.8 μs)

#0111 : 0111

Wait time = 2147 cycles (8190.2 μs)

#1000 : 1000

Wait time = 4291 cycles (16368.9 μs)

#1001 : 1001

Wait time = 8163 cycles (31139.4 μs).

: others

settings prohibited.

End of enumeration elements list.

HOCOWTCR

High-speed on-chip oscillator wait control register
address_offset : 0xA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTS : HOCO wait time settingWaiting time (sec) = setting of the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)
bits : 0 - 1 (2 bit)
access : read-write

SOPCCR

Sub Operating Power Control Register
address_offset : 0xAA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOPCM : Sub Operating Power Control Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Other than Subosc-speed mode

#1 : 1

Subosc-speed mode

End of enumeration elements list.

SOPCMTSF : Sub Operating Power Control Mode Transition Status Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transition completed

#1 : 1

During transition

End of enumeration elements list.

SBYCR

Standby Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPE : Output Port Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

In software standby mode or deep software standby mode, the address bus and bus control signals are set to the high-impedance state.

#1 : 1

In software standby mode or deep software standby mode, the address bus and bus control signals retain the output state..

End of enumeration elements list.

SSBY : Software Standby
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Sleep mode

#1 : 1

Software Standby mode (DPSBYCR.DPSBY=0) / Deep Software Standby mode (DPSBYCR.DPSBY=1)

End of enumeration elements list.

RSTSR1

Reset Status Register 1
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWDTRF : Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Independent watchdog timer reset not detected.

#1 : 1

Independent watchdog timer reset detected.

End of enumeration elements list.

WDTRF : Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer reset not detected.

#1 : 1

Watchdog timer reset detected.

End of enumeration elements list.

SWRF : Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software reset not detected.

#1 : 1

Software reset detected.

End of enumeration elements list.

RPERF : RAM Parity Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

RAM parity error reset not detected.

#1 : 1

RAM parity error reset detected.

End of enumeration elements list.

REERF : RAM ECC Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

RAM ECC error reset not detected.

#1 : 1

RAM ECC error reset detected.

End of enumeration elements list.

BUSSRF : Bus Slave MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus Slave MPU reset not detected.

#1 : 1

Bus Slave MPU reset detected.

End of enumeration elements list.

BUSMRF : Bus Master MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus Master MPU reset not detected.

#1 : 1

Bus Master MPU reset detected.

End of enumeration elements list.

SPERF : SP Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

SP error reset not detected.

#1 : 1

SP error reset detected.

End of enumeration elements list.

LVD1CR1

Voltage Monitor %s Circuit Control Register 1
address_offset : 0xE0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDTSEL : Voltage Monitor Interrupt Generation Condition Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Generate when VCC>=Vdet (rise) is detected

#01 : 01

Generate when VCC

#10 : 10

Generate when drop and rise are detected

#11 : 11

Settings prohibited

End of enumeration elements list.

IRQSEL : Voltage Monitor Interrupt Type Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Maskable interrupt

End of enumeration elements list.

LVD1SR

Voltage Monitor %s Circuit Status Register
address_offset : 0xE1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DET : Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not detected

#1 : 1

Vdet1 passage detection

End of enumeration elements list.

MON : Voltage Monitor Signal Monitor Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

VCC < Vdet

#1 : 1

VCC >= Vdet or MON bit is disabled

End of enumeration elements list.

LVD2CR1

Voltage Monitor %s Circuit Control Register 1
address_offset : 0xE2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDTSEL : Voltage Monitor Interrupt Generation Condition Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Generate when VCC>=Vdet (rise) is detected

#01 : 01

Generate when VCC

#10 : 10

Generate when drop and rise are detected

#11 : 11

Settings prohibited

End of enumeration elements list.

IRQSEL : Voltage Monitor Interrupt Type Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Maskable interrupt

End of enumeration elements list.

LVD2SR

Voltage Monitor %s Circuit Status Register
address_offset : 0xE3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

#0 : 0

Not detected

#1 : 1

Vdet1 passage detection

End of enumeration elements list.

MON : Voltage Monitor Signal Monitor Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

VCC < Vdet

#1 : 1

VCC >= Vdet or MON bit is disabled

End of enumeration elements list.

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ChipSelect

SYSTEM

Peripheral Memory Blocks

Registers

MSTPCRA

SCKDIVCR

SCKDIVCR2

SCKSCR

PLLCCR

PLLCR

BCKCR

MOSCCR

HOCOCR

MOCOCR

FLLCR1

FLLCR2

OSCSF

CKOCR

TRCKCR

PRCR

OSTDCR

DPSBYCR

DPSIER0

DPSIER1

DPSIER2

DPSIER3

DPSIFR0

DPSIFR1

DPSIFR2

DPSIFR3

DPSIEGR0

DPSIEGR1

DPSIEGR2

SYOCDCR

STCONR

OSTDSR

RSTSR0

RSTSR2

MOMCR

FWEPROR

LVCMPCR

LVDLVLR

LVD1CR0

LVD2CR0

SOSCCR

SOMCR

LOCOCR

LOCOUTCR

VBTICTLR

VBTBKR0

VBTBKR1

VBTBKR2

VBTBKR3

VBTBKR4

VBTBKR5

VBTBKR6

VBTBKR7

VBTBKR8

VBTBKR9

VBTBKR10

VBTBKR11

VBTBKR12

VBTBKR13

VBTBKR14

VBTBKR15

VBTBKR16

VBTBKR17

VBTBKR18

VBTBKR19

VBTBKR20

VBTBKR21

VBTBKR22

VBTBKR23

VBTBKR24

VBTBKR25

VBTBKR26

VBTBKR27

VBTBKR28

VBTBKR29

VBTBKR30