Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
Output Phase Switching Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UF : Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1.
bits : 0 - -1 (0 bit)
access : read-write
VF : Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1.
bits : 1 - 0 (0 bit)
access : read-write
WF : Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1.
bits : 2 - 1 (0 bit)
access : read-write
U : Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)
bits : 4 - 3 (0 bit)
access : read-only
V : Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)
bits : 5 - 4 (0 bit)
access : read-only
W : Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)
bits : 6 - 5 (0 bit)
access : read-only
EN : Enable-Phase Output Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not Output(Hi-Z external terminals).
#1 : 1
Output
End of enumeration elements list.
FB : External Feedback Signal EnableThis bit selects the input phase from the software settings and external input.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Select the external input.
#1 : 1
Select the soft setting(OPSCR.UF, VF, WF).
End of enumeration elements list.
P : Positive-Phase Output (P) Control
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Level signal output
#1 : 1
PWM signal output (PWM of GPT0)
End of enumeration elements list.
N : Negative-Phase Output (N) Control
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Level signal output
#1 : 1
PWM signal output (PWM of GPT0)
End of enumeration elements list.
INV : Invert-Phase Output Control
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Positive Logic (Active High)output
#1 : 1
Negative Logic (Active Low)output
End of enumeration elements list.
ALIGN : Input phase alignment
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Input phase is aligned to PCLK.
#1 : 1
Input phase is aligned PWM.
End of enumeration elements list.
GRP : Output disabled source selection
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : 00
Select Group A output disable source
#01 : 01
Select Group B output disable source
#10 : 10
Select Group C output disable source
#11 : 11
Select Group D output disable source
End of enumeration elements list.
GODF : Group output disable function
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
This bit function is ignored.
#1 : 1
Group disable will clear OPSCR.EN Bit.
End of enumeration elements list.
NFEN : External Input Noise Filter Enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not use a noise filter to the external input.
#1 : 1
Use a noise filter to the external input.
End of enumeration elements list.
NFCS : External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLK/1
#01 : 01
PCLK/4
#10 : 10
PCLK/16
#11 : 11
PCLK/64
End of enumeration elements list.
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