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GPT_ODC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1A Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x28 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x2A Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

GTDLYCR

GTDLYR0A

GTDLYR0B

GTDLYR1A

GTDLYR1B

GTDLYCR2

GTDLYR2A

GTDLYR2B

GTDLYR3A

GTDLYR3B

GTDLYF0A

GTDLYF0B

GTDLYF1A

GTDLYF1B

GTDLYF2A

GTDLYF2B

GTDLYF3A

GTDLYF3B


GTDLYCR

PWM Output Delay Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYCR GTDLYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLLEN DLYRST

DLLEN : DLL Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable DLL operation

#1 : 1

Enable DLL operation

End of enumeration elements list.

DLYRST : PWM Delay Generation Circuit Reset
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Reset

End of enumeration elements list.


GTDLYR0A

GTIOC%sA Rising Output Delay Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYR%s
reset_Mask : 0x0

GTDLYR0A GTDLYR0A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYR0B

GTIOC%sB Rising Output Delay Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYR%s
reset_Mask : 0x0

GTDLYR0B GTDLYR0B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnB Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYR1A

GTIOC%sA Rising Output Delay Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYR%s
reset_Mask : 0x0

GTDLYR1A GTDLYR1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYR1B

GTIOC%sB Rising Output Delay Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYR%s
reset_Mask : 0x0

GTDLYR1B GTDLYR1B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnB Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYCR2

PWM Output Delay Control Register2
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYCR2 GTDLYCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLYBS0 DLYBS1 DLYBS2 DLYBS3 DLYEN0 DLYEN1 DLYEN2 DLYEN3

DLYBS0 : PWM Delay Generation Circuit bypass for channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bypass delay generation circuit of channel 0

#1 : 1

Do not bypass delay generation circuit of channel 0.

End of enumeration elements list.

DLYBS1 : PWM Delay Generation Circuit bypass for channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bypass delay generation circuit of channel 1

#1 : 1

Do not bypass delay generation circuit of channel 1.

End of enumeration elements list.

DLYBS2 : PWM Delay Generation Circuit bypass for channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bypass delay generation circuit of channel 2

#1 : 1

Do not bypass delay generation circuit of channel 2.

End of enumeration elements list.

DLYBS3 : PWM Delay Generation Circuit bypass for channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bypass delay generation circuit of channel 3

#1 : 1

Do not bypass delay generation circuit of channel 3.

End of enumeration elements list.

DLYEN0 : PWM Delay Generation Circuit enable for channel 0
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable delay generation circuit of channel 0

#1 : 1

Disable delay generation circuit of channel 0.

End of enumeration elements list.

DLYEN1 : PWM Delay Generation Circuit enable for channel 1
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable delay generation circuit of channel 1

#1 : 1

Disable delay generation circuit of channel 1.

End of enumeration elements list.

DLYEN2 : PWM Delay Generation Circuit enable for channel 2
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable delay generation circuit of channel 2

#1 : 1

Disable delay generation circuit of channel 2.

End of enumeration elements list.

DLYEN3 : PWM Delay Generation Circuit enable for channel 3
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable delay generation circuit of channel 3

#1 : 1

Disable delay generation circuit of channel 3

End of enumeration elements list.


GTDLYR2A

GTIOC%sA Rising Output Delay Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYR%s
reset_Mask : 0x0

GTDLYR2A GTDLYR2A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYR2B

GTIOC%sB Rising Output Delay Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYR%s
reset_Mask : 0x0

GTDLYR2B GTDLYR2B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnB Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYR3A

GTIOC%sA Rising Output Delay Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYR%s
reset_Mask : 0x0

GTDLYR3A GTDLYR3A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYR3B

GTIOC%sB Rising Output Delay Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYR%s
reset_Mask : 0x0

GTDLYR3B GTDLYR3B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnB Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYF0A

GTIOC%sA Falling Output Delay Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYF%s
reset_Mask : 0x0

GTDLYF0A GTDLYF0A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Falling Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYF0B

GTIOC%sB Falling Output Delay Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYF%s
reset_Mask : 0x0

GTDLYF0B GTDLYF0B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnB Output Falling Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYF1A

GTIOC%sA Falling Output Delay Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYF%s
reset_Mask : 0x0

GTDLYF1A GTDLYF1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Falling Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYF1B

GTIOC%sB Falling Output Delay Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYF%s
reset_Mask : 0x0

GTDLYF1B GTDLYF1B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnB Output Falling Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYF2A

GTIOC%sA Falling Output Delay Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYF%s
reset_Mask : 0x0

GTDLYF2A GTDLYF2A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Falling Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYF2B

GTIOC%sB Falling Output Delay Register
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYF%s
reset_Mask : 0x0

GTDLYF2B GTDLYF2B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnB Output Falling Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYF3A

GTIOC%sA Falling Output Delay Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYF%s
reset_Mask : 0x0

GTDLYF3A GTDLYF3A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Falling Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.


GTDLYF3B

GTIOC%sB Falling Output Delay Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : GTDLYF%s
reset_Mask : 0x0

GTDLYF3B GTDLYF3B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnB Output Falling Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

: others

Delay of DLY/32 times the PCLKD period is applied.

End of enumeration elements list.



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