Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection :
address_offset : 0x140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x100 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x300 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x280 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x1A0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
IRQ Control Register %s
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
NMI Pin Interrupt Control Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIMD : NMI Detection Set
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge
#1 : 1
Rising edge
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 1 - 2 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 1 - 2 (2 bit)
access : read-write
NFCLKSEL : NMI Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
NFLTEN : NMI Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
Non-Maskable Interrupt Enable Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDTEN : IWDT Underflow/Refresh Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
IWDT underflow/refresh error interrupt is disabled.
#1 : 1
IWDT underflow/refresh error interrupt is enabled.
End of enumeration elements list.
WDTEN : WDT Underflow/Refresh Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
WDT underflow/refresh error interrupt is disabled.
#1 : 1
WDT underflow/refresh error interrupt is enabled.
End of enumeration elements list.
LVD1EN : Voltage-Monitoring 1 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Voltage-monitoring 1 interrupt is disabled.
#1 : 1
Voltage-monitoring 1 interrupt is enabled.
End of enumeration elements list.
LVD2EN : Voltage-Monitoring 2 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Voltage-monitoring 2 interrupt is disabled.
#1 : 1
Voltage-monitoring 2 interrupt is enabled.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 5 - 4 (0 bit)
access : read-write
OSTEN : Oscillation Stop Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Oscillation stop detection interrupt is disabled.
#1 : 1
Oscillation stop detection interrupt is enabled.
End of enumeration elements list.
NMIEN : NMI Pin Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
NMI pin interrupt is disabled.
#1 : 1
NMI pin interrupt is enabled.
End of enumeration elements list.
RPEEN : RAM Parity Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
RAM Parity Error interrupt is disabled.
#1 : 1
RAM Parity Error interrupt is enabled.
End of enumeration elements list.
RECCEN : RAM ECC Error Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
RAM ECC Error interrupt is disabled.
#1 : 1
RAM ECC Error interrupt is enabled.
End of enumeration elements list.
BUSSEN : MPU Bus Slave Error Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
MPU Bus Slave Error interrupt is disabled.
#1 : 1
MPU Bus Slave Error interrupt is enabled.
End of enumeration elements list.
BUSMEN : MPU Bus Master Error Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
MPU Bus Master Error interrupt is disabled.
#1 : 1
MPU Bus Master Error interrupt is enabled.
End of enumeration elements list.
SPEEN : MPU Stack Error Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
MPU Stack Error interrupt is disabled.
#1 : 1
MPU Stack Error interrupt is enabled.
End of enumeration elements list.
Non-Maskable Interrupt Status Clear Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IWDTCLR : IWDTST Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.IWDTST flag.
End of enumeration elements list.
WDTCLR : WDTST Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.WDTST flag.
End of enumeration elements list.
LVD1CLR : LVD1ST Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.LVD1ST flag.
End of enumeration elements list.
LVD2CLR : LVD2ST Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.LVD2ST flag.
End of enumeration elements list.
Reserved : The write value should be 0.
bits : 4 - 3 (0 bit)
access : write-only
Reserved : The write value should be 0.
bits : 4 - 3 (0 bit)
access : write-only
Reserved : The write value should be 0.
bits : 5 - 4 (0 bit)
access : write-only
OSTCLR : OSTST Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.OSTST flag.
End of enumeration elements list.
NMICLR : NMIST Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.NMIST flag.
End of enumeration elements list.
RPECLR : RPEST Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.RPEST flag.
End of enumeration elements list.
RECCCLR : RECCST Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.RECCST flag.
End of enumeration elements list.
BUSSCLR : BUSSST Clear
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.BUSSST flag.
End of enumeration elements list.
BUSMCLR : BUSMST Clear
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.BUSMST flag.
End of enumeration elements list.
SPECLR : SPEST Clear
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.SPEST flag.
End of enumeration elements list.
Non-Maskable Interrupt Status Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IWDTST : IWDT Underflow/Refresh Error Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
IWDT underflow/refresh error interrupt is not requested.
#1 : 1
IWDT underflow/refresh error interrupt is requested.
End of enumeration elements list.
WDTST : WDT Underflow/Refresh Error Status Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
WDT underflow/refresh error interrupt is not requested.
#1 : 1
WDT underflow/refresh error interrupt is requested.
End of enumeration elements list.
LVD1ST : Voltage-Monitoring 1 Interrupt Status Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Voltage-monitoring 1 interrupt is not requested.
#1 : 1
Voltage-monitoring 1 interrupt is requested.
End of enumeration elements list.
LVD2ST : Voltage-Monitoring 2 Interrupt Status Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
Voltage-monitoring 2 interrupt is not requested.
#1 : 1
Voltage-monitoring 2 interrupt is requested.
End of enumeration elements list.
Reserved : This bit is read as 0.
bits : 4 - 3 (0 bit)
access : read-only
Reserved : This bit is read as 0.
bits : 4 - 3 (0 bit)
access : read-only
Reserved : This bit is read as 0.
bits : 5 - 4 (0 bit)
access : read-only
OSTST : Oscillation Stop Detection Interrupt Status Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Oscillation stop detection interrupt is not requested.
#1 : 1
Oscillation stop detection interrupt is requested.
End of enumeration elements list.
NMIST : NMI Status Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
NMI pin interrupt is not requested.
#1 : 1
NMI pin interrupt is requested.
End of enumeration elements list.
RPEST : RAM Parity Error Interrupt Status Flag
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
RAM Parity Error interrupt is not requested.
#1 : 1
RAM Parity Error interrupt is requested.
End of enumeration elements list.
RECCST : RAM ECC Error Interrupt Status Flag
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
RAM ECC Error interrupt is not requested.
#1 : 1
RAM ECC Error interrupt is requested.
End of enumeration elements list.
BUSSST : MPU Bus Slave Error Interrupt Status Flag
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
MPU Bus Slave Error interrupt is not requested.
#1 : 1
MPU Bus Slave Error interrupt is requested.
End of enumeration elements list.
BUSMST : MPU Bus Master Error Interrupt Status Flag
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : 0
MPU Bus Master Error interrupt is not requested.
#1 : 1
MPU Bus Master Error interrupt is requested.
End of enumeration elements list.
SPEST : MPU Stack Error Interrupt Status Flag
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : 0
MPU Stack Error interrupt is not requested.
#1 : 1
MPU Stack Error interrupt is requested.
End of enumeration elements list.
Wake Up interrupt enable register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQWUPEN0 : IRQ0 interrupt S/W standby returns enable bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ0 interrupt is disabled
#1 : 1
S/W standby returns by IRQ0 interrupt is enabled
End of enumeration elements list.
IRQWUPEN1 : IRQ1 interrupt S/W standby returns enable bit
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ1 interrupt is disabled
#1 : 1
S/W standby returns by IRQ1 interrupt is enabled
End of enumeration elements list.
IRQWUPEN2 : IRQ2 interrupt S/W standby returns enable bit
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ2 interrupt is disabled
#1 : 1
S/W standby returns by IRQ2 interrupt is enabled
End of enumeration elements list.
IRQWUPEN3 : IRQ3 interrupt S/W standby returns enable bit
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ3 interrupt is disabled
#1 : 1
S/W standby returns by IRQ3 interrupt is enabled
End of enumeration elements list.
IRQWUPEN4 : IRQ4 interrupt S/W standby returns enable bit
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ4 interrupt is disabled
#1 : 1
S/W standby returns by IRQ4 interrupt is enabled
End of enumeration elements list.
IRQWUPEN5 : IRQ5 interrupt S/W standby returns enable bit
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ5 interrupt is disabled
#1 : 1
S/W standby returns by IRQ5 interrupt is enabled
End of enumeration elements list.
IRQWUPEN6 : IRQ6 interrupt S/W standby returns enable bit
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ6 interrupt is disabled
#1 : 1
S/W standby returns by IRQ6 interrupt is enabled
End of enumeration elements list.
IRQWUPEN7 : IRQ7 interrupt S/W standby returns enable bit
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ7 interrupt is disabled
#1 : 1
S/W standby returns by IRQ7 interrupt is enabled
End of enumeration elements list.
IRQWUPEN8 : IRQ8 interrupt S/W standby returns enable bit
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ8 interrupt is disabled
#1 : 1
S/W standby returns by IRQ8 interrupt is enabled
End of enumeration elements list.
IRQWUPEN9 : IRQ9 interrupt S/W standby returns enable bit
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ9 interrupt is disabled
#1 : 1
S/W standby returns by IRQ9 interrupt is enabled
End of enumeration elements list.
IRQWUPEN10 : IRQ10 interrupt S/W standby returns enable bit
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ10 interrupt is disabled
#1 : 1
S/W standby returns by IRQ10 interrupt is enabled
End of enumeration elements list.
IRQWUPEN11 : IRQ11 interrupt S/W standby returns enable bit
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ11 interrupt is disabled
#1 : 1
S/W standby returns by IRQ11 interrupt is enabled
End of enumeration elements list.
IRQWUPEN12 : IRQ12 interrupt S/W standby returns enable bit
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ12 interrupt is disabled
#1 : 1
S/W standby returns by IRQ12 interrupt is enabled
End of enumeration elements list.
IRQWUPEN13 : IRQ13 interrupt S/W standby returns enable bit
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ13 interrupt is disabled
#1 : 1
S/W standby returns by IRQ13 interrupt is enabled
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 14 - 13 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 14 - 13 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 15 - 14 (0 bit)
access : read-write
IWDTWUPEN : IWDT interrupt S/W standby returns enable bit
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IWDT interrupt is disabled
#1 : 1
S/W standby returns by IWDT interrupt is enabled
End of enumeration elements list.
KEYWUPEN : Key interrupt S/W standby returns enable bit
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by KEY interrupt is disabled
#1 : 1
S/W standby returns by KEY interrupt is enabled
End of enumeration elements list.
LVD1WUPEN : LVD1 interrupt S/W standby returns enable bit
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by LVD1 interrupt is disabled
#1 : 1
S/W standby returns by LVD1 interrupt is enabled
End of enumeration elements list.
LVD2WUPEN : LVD2 interrupt S/W standby returns enable bit
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by LVD2 interrupt is disabled
#1 : 1
S/W standby returns by LVD2 interrupt is enabled
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 20 - 19 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 21 - 20 (0 bit)
access : read-write
ACMPHS0WUPEN : ACMPHS0 interrupt S/W standby returns enable bit
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by ACMPHS0 interrupt is disabled
#1 : 1
S/W standby returns by ACMPHS0 interrupt is enabled
End of enumeration elements list.
RTCALMWUPEN : RTC alarm interrupt S/W standby returns enable bit
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by RTC alarm interrupt is disabled
#1 : 1
S/W standby returns by RTC alarm interrupt is enabled
End of enumeration elements list.
RTCPRDWUPEN : RCT period interrupt S/W standby returns enable bit
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by RTC period interrupt is disabled
#1 : 1
S/W standby returns by RTC period interrupt is enabled
End of enumeration elements list.
USBHSWUPEN : USBHS interrupt S/W standby returns enable bit
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by USBHS interrupt is disabled
#1 : 1
S/W standby returns by USBHS interrupt is enabled
End of enumeration elements list.
USBFSWUPEN : USBFS interrupt S/W standby returns enable bit
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by USBFS interrupt is disabled
#1 : 1
S/W standby returns by USBFS interrupt is enabled
End of enumeration elements list.
AGT1UDWUPEN : AGT1 underflow interrupt S/W standby returns enable bit
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 underflow interrupt is disabled
#1 : 1
S/W standby returns by AGT1 underflow interrupt is enabled
End of enumeration elements list.
AGT1CAWUPEN : AGT1 compare match A interrupt S/W standby returns enable bit
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 compare match A interrupt is disabled
#1 : 1
S/W standby returns by AGT1 compare match A interrupt is enabled
End of enumeration elements list.
AGT1CBWUPEN : AGT1 compare match B interrupt S/W standby returns enable bit
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 compare match B interrupt is disabled
#1 : 1
S/W standby returns by AGT1 compare match B interrupt is enabled
End of enumeration elements list.
IIC0WUPEN : IIC0 address match interrupt S/W standby returns enable bit
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IIC0 address match interrupt is disabled
#1 : 1
S/W standby returns by IIC0 address match interrupt is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
SYS Event Link Setting Register
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELS : SYS Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#000000000 : 000000000
Disable event output to the associated low-power mode module
: others
Event signal number to be linked.
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
DMAC Event Link Setting Register %s
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag for DMAC
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag for DMAC
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag for DMAC
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag for DMAC
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag for DMAC
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag for DMAC
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag for DMAC
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag for DMAC
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
INT Event Link Setting Register %s
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : Event selection to NVIC
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 2 - 2 (1 bit)
access : read-write
FCLKSEL : IRQ Digital Filter Sampling Clock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
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