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PORT1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

PCNTR1

PODR

PDR

PCNTR2

EIDR

PIDR

PCNTR3

PORR

POSR

PCNTR4

EORR

EOSR


PCNTR1

Port Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCNTR1 PCNTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDR PODR

PDR : Pmn Direction
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

#0 : 0

Input (functions as an input pin)

#1 : 1

Output (functions as an output pin).

End of enumeration elements list.

PODR : Pmn Output Data
bits : 16 - 30 (15 bit)
access : read-write

Enumeration:

#0 : 0

Low output

#1 : 1

High output.

End of enumeration elements list.


PODR

Output data register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PCNTR1
reset_Mask : 0x0

PODR PODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PODR

PODR : Pmn Output Data
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

#0 : 0

Low output

#1 : 1

High output.

End of enumeration elements list.


PDR

Data direction register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PCNTR1
reset_Mask : 0x0

PDR PDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDR

PDR : Pmn Direction
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

#0 : 0

Input (functions as an input pin)

#1 : 1

Output (functions as an output pin).

End of enumeration elements list.


PCNTR2

Port Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCNTR2 PCNTR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR EIDR

PIDR : Pmn Input Data
bits : 0 - 14 (15 bit)
access : read-only

Enumeration:

#0 : 0

Low input

#1 : 1

High input.

End of enumeration elements list.

EIDR : Pmn Event Input Data
bits : 16 - 30 (15 bit)
access : read-only

Enumeration:

#0 : 0

Low input

#1 : 1

High input.

End of enumeration elements list.


EIDR

Event input data register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PCNTR2
reset_Mask : 0x0

EIDR EIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIDR

EIDR : Pmn Event Input Data
bits : 0 - 14 (15 bit)
access : read-only

Enumeration:

#0 : 0

Low input

#1 : 1

High input.

End of enumeration elements list.


PIDR

Input data register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PCNTR2
reset_Mask : 0x0

PIDR PIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR

PIDR : Pmn Input Data
bits : 0 - 14 (15 bit)
access : read-only

Enumeration:

#0 : 0

Low input

#1 : 1

High input.

End of enumeration elements list.


PCNTR3

Port Control Register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCNTR3 PCNTR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSR PORR

POSR : Pmn Output Set
bits : 0 - 14 (15 bit)
access : write-only

Enumeration:

#0 : 0

No affect to output

#1 : 1

High output.

End of enumeration elements list.

PORR : Pmn Output Reset
bits : 16 - 30 (15 bit)
access : write-only

Enumeration:

#0 : 0

No affect to output

#1 : 1

Low output.

End of enumeration elements list.


PORR

Output set register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : PCNTR3
reset_Mask : 0x0

PORR PORR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORR

PORR : Pmn Output Reset
bits : 0 - 14 (15 bit)
access : write-only

Enumeration:

#0 : 0

No affect to output

#1 : 1

Low output.

End of enumeration elements list.


POSR

Output reset register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : PCNTR3
reset_Mask : 0x0

POSR POSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSR

POSR : Pmn Output Set
bits : 0 - 14 (15 bit)
access : write-only

Enumeration:

#0 : 0

No affect to output

#1 : 1

High output.

End of enumeration elements list.


PCNTR4

Port Control Register 4
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCNTR4 PCNTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOSR EORR

EOSR : Pmn Event Output Set
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

#0 : 0

No affect to output

#1 : 1

High output.

End of enumeration elements list.

EORR : Pmn Event Output Reset
bits : 16 - 30 (15 bit)
access : read-write

Enumeration:

#0 : 0

No affect to output

#1 : 1

Low output

End of enumeration elements list.


EORR

Event output set register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PCNTR4
reset_Mask : 0x0

EORR EORR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EORR

EORR : Pmn Event Output Reset
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

#0 : 0

No affect to output

#1 : 1

Low output

End of enumeration elements list.


EOSR

Event output reset register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PCNTR4
reset_Mask : 0x0

EOSR EOSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOSR

EOSR : Pmn Event Output Set
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

#0 : 0

No affect to output

#1 : 1

High output.

End of enumeration elements list.



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