Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xB Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x15 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
I2C Bus Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDAI : SDA Line Monitor
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
SDAn line is low.
#1 : 1
SDAn line is high.
End of enumeration elements list.
SCLI : SCL Line Monitor
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
SCLn line is low.
#1 : 1
SCLn line is high.
End of enumeration elements list.
SDAO : SDA Output Control/Monitor
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
(Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low.
#1 : 1
(Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin.
End of enumeration elements list.
SCLO : SCL Output Control/Monitor
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
(Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low.
#1 : 1
(Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin.
End of enumeration elements list.
SOWP : SCLO/SDAO Write Protect
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : 0
Enables a value to be written in SCLO bit and SDAO bit.
#1 : 1
Disables a value to be written in SCLO bit and SDAO bit.
End of enumeration elements list.
CLO : Extra SCL Clock Cycle Output
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not output an extra SCL clock cycle.
#1 : 1
Outputs an extra SCL clock cycle.
End of enumeration elements list.
IICRST : I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information).
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Releases the RIIC reset or internal reset.
#1 : 1
Initiates the RIIC reset or internal reset.
End of enumeration elements list.
ICE : I2C Bus Interface Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable (SCLn and SDAn pins in inactive state)
#1 : 1
Enable (SCLn and SDAn pins in active state)
End of enumeration elements list.
I2C Bus Control Register 2
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved : This bit is read as 0. The write value should be 0.
bits : 0 - -1 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 0 - -1 (0 bit)
access : read-write
ST : Start Condition Issuance Request Set the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state).
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not request to issue a start condition.
#1 : 1
Requests to issue a start condition.
End of enumeration elements list.
RS : Restart Condition Issuance Request Note: Do not set the RS bit to 1 while issuing a stop condition.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not request to issue a restart condition.
#1 : 1
Requests to issue a restart condition.
End of enumeration elements list.
SP : Stop Condition Issuance Request Note: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state). Note: Do not set the SP bit to 1 while a restart condition is being issued.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not request to issue a stop condition.
#1 : 1
Requests to issue a stop condition.
End of enumeration elements list.
TRS : Transmit/Receive Mode
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive mode
#1 : 1
Transmit mode
End of enumeration elements list.
MST : Master/Slave Mode
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode
#1 : 1
Master mode
End of enumeration elements list.
BBSY : Bus Busy Detection Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
The I2C bus is released (bus free state).
#1 : 1
The I2C bus is occupied (bus busy state).
End of enumeration elements list.
I2C Bus Bit Rate Low-Level Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRL : Bit Rate Low-Level Period (Low-level period of SCL clock)
bits : 0 - 3 (4 bit)
access : read-write
Reserved : This bit is read as 1. The write value should be 1.
bits : 5 - 4 (0 bit)
access : read-write
Reserved : This bit is read as 1. The write value should be 1.
bits : 5 - 4 (0 bit)
access : read-write
I2C Bus Bit Rate High-Level Register
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRH : Bit Rate High-Level Period (High-level period of SCL clock)
bits : 0 - 3 (4 bit)
access : read-write
Reserved : These bits are read as 111. The write value should be 111.
bits : 5 - 6 (2 bit)
access : read-write
I2C Bus Transmit Data Register
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICDRT : 8-bit read-write register that stores transmit data.
bits : 0 - 6 (7 bit)
access : read-write
I2C Bus Receive Data Register
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICDRR : 8-bit register that stores the received data
bits : 0 - 6 (7 bit)
access : read-only
I2C Bus Mode Register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BC : Bit Counter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
9 bits
#001 : 001
2 bits
#010 : 010
3 bits
#011 : 011
4 bits
#100 : 100
5 bits
#101 : 101
6 bits
#110 : 110
7 bits
#111 : 111
8 bits
End of enumeration elements list.
BCWP : BC Write Protect (This bit is read as 1.)
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : 0
Enables a value to be written in the BC[2:0] bits.
#1 : 1
Disables a value to be written in the BC[2:0] bits.
End of enumeration elements list.
CKS : Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
PCLKB/1 clock
#001 : 001
PCLKB/2 clock
#010 : 010
PCLKB/4 clock
#011 : 011
PCLKB/8 clock
#100 : 100
PCLKB/16 clock
#101 : 101
PCLKB/32 clock
#110 : 110
PCLKB/64 clock
#111 : 111
PCLKB/128 clock
End of enumeration elements list.
MTWP : MST/TRS Write Protect
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables writing to the MST and TRS bits in ICCR2.
#1 : 1
Enables writing to the MST and TRS bits in ICCR2.
End of enumeration elements list.
I2C Bus Mode Register 2
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMOS : Timeout Detection Time Selection
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Long mode is selected.
#1 : 1
Short mode is selected.
End of enumeration elements list.
TMOL : Timeout L Count Control
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Count is disabled while the SCLn line is at a low level.
#1 : 1
Count is enabled while the SCLn line is at a low level.
End of enumeration elements list.
TMOH : Timeout H Count Control
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Count is disabled while the SCLn line is at a high level.
#1 : 1
Count is enabled while the SCLn line is at a high level.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
SDDL : SDA Output Delay Counter
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
No output delay
#001 : 001
1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1)
#010 : 010
2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1)
#011 : 011
3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1)
#100 : 100
4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1)
#101 : 101
5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1)
#110 : 110
6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)
#111 : 111
7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)
End of enumeration elements list.
DLCS : SDA Output Delay Clock Source Selection
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter.
#1 : 1
The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter.
End of enumeration elements list.
I2C Bus Mode Register 3
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NF : Noise Filter Stage Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Noise of up to one fIIC cycle is filtered out (single-stage filter).
#01 : 01
Noise of up to two fIIC cycles is filtered out (2-stage filter).
#10 : 10
Noise of up to three fIIC cycles is filtered out (3-stage filter).
#11 : 11
Noise of up to four fIIC cycles is filtered out (4-stage filter)
End of enumeration elements list.
ACKBR : Receive Acknowledge
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
A 0 is received as the acknowledge bit (ACK reception).
#1 : 1
A 1 is received as the acknowledge bit (NACK reception).
End of enumeration elements list.
ACKBT : Transmit Acknowledge
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
A 0 is sent as the acknowledge bit (ACK transmission).
#1 : 1
A 1 is sent as the acknowledge bit (NACK transmission).
End of enumeration elements list.
ACKWP : ACKBT Write Protect
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Modification of the ACKBT bit is disabled.
#1 : 1
Modification of the ACKBT bit is enabled.
End of enumeration elements list.
RDRFS : RDRF Flag Set Timing Selection
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)
#1 : 1
The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.)
End of enumeration elements list.
WAIT : WAIT Note: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand.
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)
#1 : 1
WAIT (The period between ninth clock cycle and first clock cycle is held low.)
End of enumeration elements list.
SMBS : SMBus/I2C Bus Selection
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The I2C bus is selected.
#1 : 1
The SMBus is selected.
End of enumeration elements list.
I2C Bus Function Enable Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMOE : Timeout Function Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The timeout function is disabled.
#1 : 1
The timeout function is enabled.
End of enumeration elements list.
MALE : Master Arbitration-Lost Detection Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Master arbitration-lost detection is disabled.
#1 : 1
Master arbitration-lost detection is enabled.
End of enumeration elements list.
NALE : NACK Transmission Arbitration-Lost Detection Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
NACK transmission arbitration-lost detection is disabled.
#1 : 1
NACK transmission arbitration-lost detection is enabled.
End of enumeration elements list.
SALE : Slave Arbitration-Lost Detection Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave arbitration-lost detection is disabled.
#1 : 1
Slave arbitration-lost detection is enabled.
End of enumeration elements list.
NACKE : NACK Reception Transfer Suspension Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transfer operation is not suspended during NACK reception (transfer suspension disabled).
#1 : 1
Transfer operation is suspended during NACK reception (transfer suspension enabled).
End of enumeration elements list.
NFE : Digital Noise Filter Circuit Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No digital noise filter circuit is used.
#1 : 1
A digital noise filter circuit is used.
End of enumeration elements list.
SCLE : SCL Synchronous Circuit Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No SCL synchronous circuit is used.
#1 : 1
An SCL synchronous circuit is used.
End of enumeration elements list.
FMPE : Fast-mode Plus Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No Fm+ slope control circuit is used for the SCLn pin and SDAn pin.
#1 : 1
An Fm+ slope control circuit is used for the SCLn pin and SDAn pin.
End of enumeration elements list.
I2C Bus Status Enable Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR0E : Slave Address Register 0 Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave address in SARL0 and SARU0 is disabled.
#1 : 1
Slave address in SARL0 and SARU0 is enabled.
End of enumeration elements list.
SAR1E : Slave Address Register 1 Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave address in SARL1 and SARU1 is disabled.
#1 : 1
Slave address in SARL1 and SARU1 is enabled.
End of enumeration elements list.
SAR2E : Slave Address Register 2 Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave address in SARL2 and SARU2 is disabled.
#1 : 1
Slave address in SARL2 and SARU2 is enabled
End of enumeration elements list.
GCAE : General Call Address Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
General call address detection is disabled.
#1 : 1
General call address detection is enabled.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
DIDE : Device-ID Address Detection Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Device-ID address detection is disabled.
#1 : 1
Device-ID address detection is enabled.
End of enumeration elements list.
HOAE : Host Address Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Host address detection is disabled.
#1 : 1
Host address detection is enabled.
End of enumeration elements list.
I2C Bus Interrupt Enable Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMOIE : Timeout Interrupt Request Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Timeout interrupt request (TMOI) is disabled.
#1 : 1
Timeout interrupt request (TMOI) is enabled.
End of enumeration elements list.
ALIE : Arbitration-Lost Interrupt Request Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Arbitration-lost interrupt request (ALI) is disabled.
#1 : 1
Arbitration-lost interrupt request (ALI) is enabled.
End of enumeration elements list.
STIE : Start Condition Detection Interrupt Request Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Start condition detection interrupt request (STI) is disabled.
#1 : 1
Start condition detection interrupt request (STI) is enabled.
End of enumeration elements list.
SPIE : Stop Condition Detection Interrupt Request Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stop condition detection interrupt request (SPI) is disabled.
#1 : 1
Stop condition detection interrupt request (SPI) is enabled.
End of enumeration elements list.
NAKIE : NACK Reception Interrupt Request Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
NACK reception interrupt request (NAKI) is disabled.
#1 : 1
NACK reception interrupt request (NAKI) is enabled.
End of enumeration elements list.
RIE : Receive Data Full Interrupt Request Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive data full interrupt request (RXI) is disabled.
#1 : 1
Receive data full interrupt request (RXI) is enabled.
End of enumeration elements list.
TEIE : Transmit End Interrupt Request Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit end interrupt request (TEI) is disabled.
#1 : 1
Transmit end interrupt request (TEI) is enabled.
End of enumeration elements list.
TIE : Transmit Data Empty Interrupt Request Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data empty interrupt request (TXI) is disabled.
#1 : 1
Transmit data empty interrupt request (TXI) is enabled.
End of enumeration elements list.
I2C Bus Status Register 1
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AAS0 : Slave Address 0 Detection Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave address 0 is not detected.
#1 : 1
Slave address 0 is detected.
End of enumeration elements list.
AAS1 : Slave Address 1 Detection Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave address 1 is not detected.
#1 : 1
Slave address 1 is detected.
End of enumeration elements list.
AAS2 : Slave Address 2 Detection Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave address 2 is not detected.
#1 : 1
Slave address 2 is detected
End of enumeration elements list.
GCA : General Call Address Detection Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
General call address is not detected.
#1 : 1
General call address is detected.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
DID : Device-ID Address Detection Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Device-ID command is not detected.
#1 : 1
Device-ID command is detected.
End of enumeration elements list.
HOA : Host Address Detection Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Host address is not detected.
#1 : 1
Host address is detected.
End of enumeration elements list.
I2C Bus Status Register 2
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMOF : Timeout Detection Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Timeout is not detected.
#1 : 1
Timeout is detected.
End of enumeration elements list.
AL : Arbitration-Lost Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Arbitration is not lost.
#1 : 1
Arbitration is lost.
End of enumeration elements list.
START : Start Condition Detection Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Start condition is not detected.
#1 : 1
Start condition is detected.
End of enumeration elements list.
STOP : Stop Condition Detection Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stop condition is not detected.
#1 : 1
Stop condition is detected.
End of enumeration elements list.
NACKF : NACK Detection Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
NACK is not detected.
#1 : 1
NACK is detected.
End of enumeration elements list.
RDRF : Receive Data Full Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
ICDRR contains no receive data.
#1 : 1
ICDRR contains receive data.
End of enumeration elements list.
TEND : Transmit End Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data is being transmitted.
#1 : 1
Data has been transmitted.
End of enumeration elements list.
TDRE : Transmit Data Empty Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
ICDRT contains transmit data.
#1 : 1
ICDRT contains no transmit data.
End of enumeration elements list.
Slave Address Register L%s
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVA : A slave address is set. 7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] }
bits : 0 - 6 (7 bit)
access : read-write
Slave Address Register U%s
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FS : 7-Bit/10-Bit Address Format Selection
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The 7-bit address format is selected.
#1 : 1
The 10-bit address format is selected.
End of enumeration elements list.
SVA8 : 10-Bit Address(bit8)
bits : 1 - 0 (0 bit)
access : read-write
SVA9 : 10-Bit Address(bit9)
bits : 2 - 1 (0 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
Slave Address Register L%s
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVA : A slave address is set. 7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] }
bits : 0 - 6 (7 bit)
access : read-write
Slave Address Register U%s
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FS : 7-Bit/10-Bit Address Format Selection
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The 7-bit address format is selected.
#1 : 1
The 10-bit address format is selected.
End of enumeration elements list.
SVA8 : 10-Bit Address(bit8)
bits : 1 - 0 (0 bit)
access : read-write
SVA9 : 10-Bit Address(bit9)
bits : 2 - 1 (0 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
Slave Address Register L%s
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVA : A slave address is set. 7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] }
bits : 0 - 6 (7 bit)
access : read-write
Slave Address Register U%s
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FS : 7-Bit/10-Bit Address Format Selection
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The 7-bit address format is selected.
#1 : 1
The 10-bit address format is selected.
End of enumeration elements list.
SVA8 : 10-Bit Address(bit8)
bits : 1 - 0 (0 bit)
access : read-write
SVA9 : 10-Bit Address(bit9)
bits : 2 - 1 (0 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
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