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A/D Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBLANS : Double Trigger Channel Select These bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected.
bits : 0 - 3 (4 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 5 - 4 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 5 - 4 (0 bit)
access : read-write
GBADIE : Group B Scan End Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables ADC120_GBADI interrupt generation upon group B scan completion.
#1 : 1
Enables ADC120_GBADI interrupt generation upon group B scan completion.
End of enumeration elements list.
DBLE : Double Trigger Mode Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Double trigger mode non-selection
#1 : 1
Double trigger mode selection
End of enumeration elements list.
EXTRG : Trigger Select
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
A/D conversion is started by the synchronous trigger (ELC).
#1 : 1
A/D conversion is started by the asynchronous trigger (ADTRG0).
End of enumeration elements list.
TRGE : Trigger Start Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables A/D conversion to be started by the synchronous or asynchronous trigger.
#1 : 1
Enables A/D conversion to be started by the synchronous or asynchronous trigger.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 10 - 9 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write
ADCS : Scan Mode Select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#00 : 00
Single scan mode
#01 : 01
Group scan mode
#10 : 10
Continuous scan mode
#11 : 11
Setting prohibited
End of enumeration elements list.
ADST : A/D Conversion Start
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stops A/D conversion process.
#1 : 1
Starts A/D conversion process.
End of enumeration elements list.
A/D Conversion Start Trigger Select Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRSB : A/D Conversion Start Trigger Select for Group B Select the A/D conversion start trigger for group B in group scan mode.
bits : 0 - 4 (5 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
TRSA : A/D Conversion Start Trigger Select Select the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected.
bits : 8 - 12 (5 bit)
access : read-write
A/D Conversion Extended Input Control Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSSAD : Temperature Sensor Output A/D converted Value Addition/Average Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor output A/D-converted value addition/average mode is not selected.
#1 : 1
Temperature sensor output A/D-converted value addition/average mode is selected.
End of enumeration elements list.
OCSAD : Internal Reference Voltage A/D converted Value Addition/Average Mode Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Internal reference voltage A/D-converted value addition/average mode is not selected.
#1 : 1
Internal reference voltage A/D-converted value addition/average mode is selected.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 2 - 6 (5 bit)
access : read-write
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 2 - 6 (5 bit)
access : read-write
TSSA : Temperature Sensor Output A/D Conversion Select
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
The temperature sensor output is not selected.
#1 : 1
The temperature sensor output is selected.
End of enumeration elements list.
OCSA : Internal Reference Voltage A/D Conversion Select
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
The internal reference voltage is not selected.
#1 : 1
The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode.
End of enumeration elements list.
TSSB : Temperature Sensor Output A/D Conversion Select for Group B
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
The temperature sensor output is not selected.
#1 : 1
The temperature sensor output is not selected for group B in group scan mode.
End of enumeration elements list.
OCSB : Internal Reference Voltage A/D Conversion Select for Group B
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
The internal reference voltage is not selected.
#1 : 1
The internal reference voltage is selected for group B in group scan mode.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 12 - 11 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 14 - 13 (0 bit)
access : read-write
A/D Channel Select Register B0
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANSB00 : AN000 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN000 is not subjected to conversion.
#1 : 1
AN000 is subjected to conversion.
End of enumeration elements list.
ANSB01 : AN001 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN001 is not subjected to conversion.
#1 : 1
AN001 is subjected to conversion.
End of enumeration elements list.
ANSB02 : AN002 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN002 is not subjected to conversion.
#1 : 1
AN002 is subjected to conversion.
End of enumeration elements list.
ANSB03 : AN003 Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN003 is not subjected to conversion.
#1 : 1
AN003 is subjected to conversion.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
ANSB05 : AN005 Select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN005 is not subjected to conversion.
#1 : 1
AN005 is subjected to conversion.
End of enumeration elements list.
ANSB06 : AN006 Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN006 is not subjected to conversion.
#1 : 1
AN006 is subjected to conversion.
End of enumeration elements list.
ANSB07 : AN007 Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN007 is not subjected to conversion.
#1 : 1
AN007 is subjected to conversion.
End of enumeration elements list.
A/D Channel Select Register B1
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANSB16 : AN016 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN016 is not subjected to conversion.
#1 : 1
AN016 is subjected to conversion.
End of enumeration elements list.
ANSB17 : AN017 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN017 is not subjected to conversion.
#1 : 1
AN017 is subjected to conversion.
End of enumeration elements list.
ANSB18 : AN018 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN018 is not subjected to conversion.
#1 : 1
AN018 is subjected to conversion.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
ANSB20 : AN020 Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN020 is not subjected to conversion.
#1 : 1
AN020 is subjected to conversion.
End of enumeration elements list.
A/D Data Duplication Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDBLDR : This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode.
bits : 0 - 14 (15 bit)
access : read-only
A/D Temperature Sensor Data Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADTSDR : This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output.
bits : 0 - 14 (15 bit)
access : read-only
A/D Programmable Gain Amplifier Control Register
address_offset : 0x1A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P000SEL0 : A through amplifier is enable for PGA P000
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not through the PGA in amplifier
#1 : 1
I will through in the PGA amplifier.
End of enumeration elements list.
P000SEL1 : The amplifier passing is enable for PGA P000
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
By way of the amplifier in PGA.
#1 : 1
Note 1 that by way of amplifier in PGA
End of enumeration elements list.
P000ENAMP : Amplifier enable bit for PGA P000
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The amplifier in PGA is not used.
#1 : 1
The amplifier in PGA is used.
End of enumeration elements list.
P000GEN : PGA P000 gain setting and enable bit
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
The gain setting is invalidated (AIN is not input in PGA).
#1 : 1
The gain setting is effectively done (AIN is input in PGA).
End of enumeration elements list.
P001SEL0 : A through amplifier is enable for PGA P001
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not through the PGA in amplifier
#1 : 1
I will through in the PGA amplifier.
End of enumeration elements list.
P001SEL1 : The amplifier passing is enable for PGA P001
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
By way of the amplifier in PGA.
#1 : 1
Note 1 that by way of amplifier in PGA
End of enumeration elements list.
P001ENAMP : Amplifier enable bit for PGA P001
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The amplifier in PGA is not used.
#1 : 1
The amplifier in PGA is used.
End of enumeration elements list.
P001GEN : PGA P001 gain setting and enable bit
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The gain setting is invalidated (AIN is not input in PGA).
#1 : 1
The gain setting is effectively done (AIN is input in PGA).
End of enumeration elements list.
P002SEL0 : A through amplifier is enable for PGA P002
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not through the PGA in amplifier
#1 : 1
I will through in the PGA amplifier.
End of enumeration elements list.
P002SEL1 : The amplifier passing is enable for PGA P002
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
By way of the amplifier in PGA.
#1 : 1
Note 1 that by way of amplifier in PGA
End of enumeration elements list.
P002ENAMP : Amplifier enable bit for PGA P002
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
The amplifier in PGA is not used.
#1 : 1
The amplifier in PGA is used.
End of enumeration elements list.
P002GEN : PGA P002 gain setting and enable bit
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
The gain setting is invalidated (AIN is not input in PGA).
#1 : 1
The gain setting is effectively done (AIN is input in PGA).
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 12 - 11 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 12 - 11 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 13 - 12 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 14 - 13 (0 bit)
access : read-write
A/D Programmable Gain Amplifier Gain Setting Register 0
address_offset : 0x1A2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P000GAIN : PGA P000 gain setting bit. The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
x 2.000 (ADPGADDCR0.P000DEN=0)
#0001 : 0001
x 2.500 (ADPGADDCR0.P000DEN=0) / x 1.500 (ADPGADDCR0.P000DEN=1)
#0010 : 0010
x 2.667 (ADPGADDCR0.P000DEN=0)
#0011 : 0011
x 2.857 (ADPGADDCR0.P000DEN=0)
#0100 : 0100
x 3.077 (ADPGADDCR0.P000DEN=0)
#0101 : 0101
x 3.333 (ADPGADDCR0.P000DEN=0) / x 2.333 (ADPGADDCR0.P000DEN=1)
#0110 : 0110
x 3.636 (ADPGADDCR0.P000DEN=0)
#0111 : 0111
x 4.000 (ADPGADDCR0.P000DEN=0)
#1000 : 1000
x 4.444 (ADPGADDCR0.P000DEN=0)
#1001 : 1001
x 5.000 (ADPGADDCR0.P000DEN=0) / x 4.00 (ADPGADDCR0.P000DEN=1)
#1010 : 1010
x 5.714 (ADPGADDCR0.P000DEN=0)
#1011 : 1011
x 6.667 (ADPGADDCR0.P000DEN=0) / x 5.667 (ADPGADDCR0.P000DEN=1)
#1100 : 1100
x 8.000 (ADPGADDCR0.P000DEN=0)
#1101 : 1101
x 10.000 (ADPGADDCR0.P000DEN=0)
#1110 : 1110
x 13.333 (ADPGADDCR0.P000DEN=0)
: others
Setting prohibited
End of enumeration elements list.
P001GAIN : PGA P001 gain setting bit. The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
x 2.000 (ADPGADDCR0.P001DEN=0)
#0001 : 0001
x 2.500 (ADPGADDCR0.P001DEN=0) / x 1.500 (ADPGADDCR0.P001DEN=1)
#0010 : 0010
x 2.667 (ADPGADDCR0.P001DEN=0)
#0011 : 0011
x 2.857 (ADPGADDCR0.P001DEN=0)
#0100 : 0100
x 3.077 (ADPGADDCR0.P001DEN=0)
#0101 : 0101
x 3.333 (ADPGADDCR0.P001DEN=0) / x 2.333 (ADPGADDCR0.P001DEN=1)
#0110 : 0110
x 3.636 (ADPGADDCR0.P001DEN=0)
#0111 : 0111
x 4.000 (ADPGADDCR0.P001DEN=0)
#1000 : 1000
x 4.444 (ADPGADDCR0.P001DEN=0)
#1001 : 1001
x 5.000 (ADPGADDCR0.P001DEN=0) / x 4.00 (ADPGADDCR0.P001DEN=1)
#1010 : 1010
x 5.714 (ADPGADDCR0.P001DEN=0)
#1011 : 1011
x 6.667 (ADPGADDCR0.P001DEN=0) / x 5.667 (ADPGADDCR0.P001DEN=1)
#1100 : 1100
x 8.000 (ADPGADDCR0.P001DEN=0)
#1101 : 1101
x 10.000 (ADPGADDCR0.P001DEN=0)
#1110 : 1110
x 13.333 (ADPGADDCR0.P001DEN=0)
: others
Setting prohibited
End of enumeration elements list.
P002GAIN : PGA P002 gain setting bit. The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
x 2.000 (ADPGADDCR0.P002DEN=0)
#0001 : 0001
x 2.500 (ADPGADDCR0.P002DEN=0) / x 1.500 (ADPGADDCR0.P002DEN=1)
#0010 : 0010
x 2.667 (ADPGADDCR0.P002DEN=0)
#0011 : 0011
x 2.857 (ADPGADDCR0.P002DEN=0)
#0100 : 0100
x 3.077 (ADPGADDCR0.P002DEN=0)
#0101 : 0101
x 3.333 (ADPGADDCR0.P002DEN=0) / x 2.333 (ADPGADDCR0.P002DEN=1)
#0110 : 0110
x 3.636 (ADPGADDCR0.P002DEN=0)
#0111 : 0111
x 4.000 (ADPGADDCR0.P002DEN=0)
#1000 : 1000
x 4.444 (ADPGADDCR0.P002DEN=0)
#1001 : 1001
x 5.000 (ADPGADDCR0.P002DEN=0) / x 4.00 (ADPGADDCR0.P002DEN=1)
#1010 : 1010
x 5.714 (ADPGADDCR0.P002DEN=0)
#1011 : 1011
x 6.667 (ADPGADDCR0.P002DEN=0) / x 5.667 (ADPGADDCR0.P002DEN=1)
#1100 : 1100
x 8.000 (ADPGADDCR0.P002DEN=0)
#1101 : 1101
x 10.000 (ADPGADDCR0.P002DEN=0)
#1110 : 1110
x 13.333 (ADPGADDCR0.P002DEN=0)
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
A/D Programmable Gain Amplifier Differential Input Control Register
address_offset : 0x1B0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P000DG : P000 Differential Input Gain Setting NOTE: When these bits are used, set {P000DEN, P000GEN} to 11b.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
x 1.5
#01 : 01
x 2.333
#10 : 10
x 4.0
#11 : 11
x 5.667
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 2 - 1 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 2 - 1 (0 bit)
access : read-write
P000DEN : P000 Differential Input Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Differential input is disabled.
#1 : 1
Differential input is enabled.
End of enumeration elements list.
P001DG : P001 Differential Input Gain Setting NOTE: When these bits are used, set {P001DEN, P001GEN} to 11b.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
x 1.5
#01 : 01
x 2.333
#10 : 10
x 4.0
#11 : 11
x 5.667
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
P001DEN : P001 Differential Input Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Differential input is disabled.
#1 : 1
Differential input is enabled.
End of enumeration elements list.
P002DG : P002 Differential Input Gain Setting NOTE: When these bits are used, set {P002DEN, P002GEN} to 11b.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
x 1.5
#01 : 01
x 2.333
#10 : 10
x 4.0
#11 : 11
x 5.667
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 10 - 9 (0 bit)
access : read-write
P002DEN : P002 Differential Input Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Differential input is disabled.
#1 : 1
Differential input is enabled.
End of enumeration elements list.
P003DG : P003 Differential Input Gain Setting NOTE: When these bits are used, set {P003DEN, P003GEN} to 11b.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : 00
x 1.5
#01 : 01
x 2.333
#10 : 10
x 4.0
#11 : 11
x 5.667
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 14 - 13 (0 bit)
access : read-write
A/D Internal Reference Voltage Data Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADOCDR : This is a 16-bit read-only register for storing the A/D result of internal reference voltage.
bits : 0 - 14 (15 bit)
access : read-only
A/D Self-Diagnosis Data Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AD : A/D-converted value (right-justified) NOTE: Unused bits in the AD bit field are fixed 0
bits : 0 - 10 (11 bit)
access : read-only
Reserved : These bits are read as 00.
bits : 12 - 12 (1 bit)
access : read-only
DIAGST : Self-Diagnosis Status
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#00 : 00
Self-diagnosis has never been executed since power-on.
#01 : 01
Self-diagnosis using the voltage of 0 V has been executed.
#10 : 10
Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed.
#11 : 11
Self-diagnosis using the voltage of reference power supply(VREFH) has been executed.
End of enumeration elements list.
A/D Data Register %s
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Channel Select Register A0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANSA00 : AN000 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN000 is not subjected to conversion.
#1 : 1
AN000 is subjected to conversion.
End of enumeration elements list.
ANSA01 : AN001 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN001 is not subjected to conversion.
#1 : 1
AN001 is subjected to conversion.
End of enumeration elements list.
ANSA02 : AN002 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN002 is not subjected to conversion.
#1 : 1
AN002 is subjected to conversion.
End of enumeration elements list.
ANSA03 : AN003 Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN003 is not subjected to conversion.
#1 : 1
AN003 is subjected to conversion.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
ANSA05 : AN005 Select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN005 is not subjected to conversion.
#1 : 1
AN005 is subjected to conversion.
End of enumeration elements list.
ANSA06 : AN006 Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN006 is not subjected to conversion.
#1 : 1
AN006 is subjected to conversion.
End of enumeration elements list.
ANSA07 : AN007 Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN007 is not subjected to conversion.
#1 : 1
AN007 is subjected to conversion.
End of enumeration elements list.
A/D Data Register %s
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Register %s
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
bits : 0 - 14 (15 bit)
access : read-only
A/D Channel Select Register A1
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANSA16 : AN016 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN016 is not subjected to conversion.
#1 : 1
AN016 is subjected to conversion.
End of enumeration elements list.
ANSA17 : AN017 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN017 is not subjected to conversion.
#1 : 1
AN017 is subjected to conversion.
End of enumeration elements list.
ANSA18 : AN018 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN018 is not subjected to conversion.
#1 : 1
AN018 is subjected to conversion.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
ANSA20 : AN020 Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN020 is not subjected to conversion.
#1 : 1
AN020 is subjected to conversion.
End of enumeration elements list.
A/D Sample and Hold Circuit Control Register
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTSH : Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting Set the sampling time (4 to 255 states)
bits : 0 - 6 (7 bit)
access : read-write
SHANS0 : AN000 sample-and-hold circuit Select
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bypass the sample-and-hold circuit.
#1 : 1
Use the sample-and-hold circuit.
End of enumeration elements list.
SHANS1 : AN001 sample-and-hold circuit Select
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bypass the sample-and-hold circuit.
#1 : 1
Use the sample-and-hold circuit.
End of enumeration elements list.
SHANS2 : AN002 sample-and-hold circuit Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bypass the sample-and-hold circuit.
#1 : 1
Use the sample-and-hold circuit.
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
A/D Disconnection Detection Control Register
address_offset : 0x7A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNDIS : The charging time
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Disconnection detection is disabled
#0001 : 0001
Setting prohibited
: others
( 1 / ADCLK ) x ADNDIS
End of enumeration elements list.
PCHG : Selection of Precharge or Discharge
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Discharge
#1 : 1
Precharge
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write
A/D Sample and Hold Operation Mode Select Register
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHMD : Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Sampling by channel-dedicated sample-and-hold circuit is disable.
#1 : 1
Sampling by channel-dedicated sample-and-hold circuit is enable.
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 1 - 6 (6 bit)
access : read-write
A/D-Converted Value Addition/Average Channel Select Register 0
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADS00 : A/D-Converted Value Addition/Average Channel AN000 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN000 is not selected.
#1 : 1
AN000 is selected.
End of enumeration elements list.
ADS01 : A/D-Converted Value Addition/Average Channel AN001 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN001 is not selected.
#1 : 1
AN001 is selected.
End of enumeration elements list.
ADS02 : A/D-Converted Value Addition/Average Channel AN002 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN002 is not selected.
#1 : 1
AN002 is selected.
End of enumeration elements list.
ADS03 : A/D-Converted Value Addition/Average Channel AN003 Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN003 is not selected.
#1 : 1
AN003 is selected.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
ADS05 : A/D-Converted Value Addition/Average Channel AN005 Select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN005 is not selected.
#1 : 1
AN005 is selected.
End of enumeration elements list.
ADS06 : A/D-Converted Value Addition/Average Channel AN006 Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN006 is not selected.
#1 : 1
AN006 is selected.
End of enumeration elements list.
ADS07 : A/D-Converted Value Addition/Average Channel AN007 Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN007 is not selected.
#1 : 1
AN007 is selected.
End of enumeration elements list.
A/D Group Scan Priority Control Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PGS : Group A priority control setting bit. Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Operation is without group A priority control
#1 : 1
Operation is with group A priority control
End of enumeration elements list.
GBRSCN : Group B Restart Setting (Enabled only when PGS = 1. Reserved when PGS = 0.)
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Scanning for group B is not restarted after having been discontinued due to group A priority control.
#1 : 1
Scanning for group B is restarted after having been discontinued due to group A priority control.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 2 - 6 (5 bit)
access : read-write
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 2 - 6 (5 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 8 - 7 (0 bit)
access : read-write
GBRP : Group B Single Scan Continuous Start (Enabled only when PGS = 1. Reserved when PGS = 0.) Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit.
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single scan for group B is not continuously activated.
#1 : 1
Single scan for group B is continuously activated.
End of enumeration elements list.
A/D Data Duplication Register A
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDBLDRA : This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode.
bits : 0 - 14 (15 bit)
access : read-only
A/D Data Duplication Register B
address_offset : 0x86 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDBLDRB : This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode.
bits : 0 - 14 (15 bit)
access : read-only
A/D Compare Function Window A/B Status Monitor Register
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MONCOMB : Combination result monitor This bit indicates the combination result. This bit is valid when both window A operation and window B operation are enabled.
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Window A / window B composite conditions are not met.
#1 : 1
Window A / window B composite conditions are met.
End of enumeration elements list.
Reserved : These bits are read as 000.
bits : 1 - 2 (2 bit)
access : read-only
Reserved : These bits are read as 000.
bits : 1 - 2 (2 bit)
access : read-only
MONCMPA : Comparison Result Monitor A
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Window A comparison conditions are not met.
#1 : 1
Window A comparison conditions are met.
End of enumeration elements list.
MONCMPB : Comparison Result Monitor B
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Window B comparison conditions are not met.
#1 : 1
Window B comparison conditions are met.
End of enumeration elements list.
A/D Compare Function Control Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPAB : Window A/B Composite Conditions Setting NOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
S12ADWMELC is output when window A comparison conditions are met OR window B comparison conditions are met. S12ADWUMELC is output in other cases.
#01 : 01
S12ADWMELC is output when window A comparison conditions are met EXOR window B comparison conditions are met. S12ADWUMELC is output in other cases.
#10 : 10
S12ADWMELC is output when window A comparison conditions are met and window B comparison conditions are met. S12ADWUMELC is output in other cases.
#11 : 11
Setting prohibited.
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 2 - 7 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 2 - 7 (6 bit)
access : read-write
CMPBE : Compare Window B Operation Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Compare window B operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled.
#1 : 1
Compare window B operation is enabled.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 10 - 9 (0 bit)
access : read-write
CMPAE : Compare Window A Operation Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Compare window A operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled.
#1 : 1
Compare window A operation is enabled.
End of enumeration elements list.
CMPBIE : Compare B Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
S12ADCMPBIi interrupt is disabled when comparison conditions (window B) are met.
#1 : 1
S12ADCMPBIi interrupt is enabled when comparison conditions (window B) are met.
End of enumeration elements list.
WCMPE : Window Function Setting
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result.
#1 : 1
Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result.
End of enumeration elements list.
CMPAIE : Compare A Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
S12ADCMPAIi interrupt is disabled when comparison conditions (window A) are met.
#1 : 1
S12ADCMPAIi interrupt is enabled when comparison conditions (window A) are met.
End of enumeration elements list.
A/D Compare Function Window A Extended Input Select Register
address_offset : 0x92 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPTSA : Temperature sensor output Compare selection bit.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Excludes the temperature sensor output from the compare window A target range.
#1 : 1
Includes the temperature sensor output in the compare window A target range.
End of enumeration elements list.
CMPOCA : Internal reference voltage Compare selection bit.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Excludes the internal reference voltage from the compare window A target range.
#1 : 1
Includes the internal reference voltage in the compare window A target range.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 2 - 6 (5 bit)
access : read-write
A/D Compare Function Window A Extended Input Comparison Condition Setting Register
address_offset : 0x93 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPLTSA : Compare Window A Temperature Sensor Output Comparison Condition Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1).
#1 : 1
ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1).
End of enumeration elements list.
CMPLOCA : Compare Window A Internal Reference Voltage Comparison Condition Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1)
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 2 - 6 (5 bit)
access : read-write
A/D Compare Function Window A Channel Select Register 0
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPCHA00 : Compare Window A Channel AN000 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function for AN000
#1 : 1
Enable compare function for AN000
End of enumeration elements list.
CMPCHA01 : Compare Window A Channel AN001 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function for AN001
#1 : 1
Enable compare function for AN001
End of enumeration elements list.
CMPCHA02 : Compare Window A Channel AN002 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function for AN002
#1 : 1
Enable compare function for AN002
End of enumeration elements list.
CMPCHA03 : Compare Window A Channel AN003 Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function for AN003
#1 : 1
Enable compare function for AN003
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
CMPCHA05 : Compare Window A Channel AN005 Select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function for AN005
#1 : 1
Enable compare function for AN005
End of enumeration elements list.
CMPCHA06 : Compare Window A Channel AN006 Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function for AN006
#1 : 1
Enable compare function for AN006
End of enumeration elements list.
CMPCHA07 : Compare Window A Channel AN007 Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function for AN007
#1 : 1
Enable compare function for AN007
End of enumeration elements list.
A/D Compare Function Window A Channel Select Register 1
address_offset : 0x96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPCHA16 : AN016 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Excludes AN016 from the compare window A target range.
#1 : 1
Includes AN016 from the compare window A target range.
End of enumeration elements list.
CMPCHA17 : AN017 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Excludes AN017 from the compare window A target range.
#1 : 1
Includes AN017 from the compare window A target range.
End of enumeration elements list.
CMPCHA18 : AN018 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Excludes AN018 from the compare window A target range.
#1 : 1
Includes AN018 from the compare window A target range.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
CMPCHA20 : AN020 Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Excludes AN020 from the compare window A target range.
#1 : 1
Includes AN020 from the compare window A target range.
End of enumeration elements list.
A/D Compare Function Window A Comparison Condition Setting Register 0
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPLCHA00 : Comparison condition of AN000
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
CMPLCHA01 : Comparison condition of AN001
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
CMPLCHA02 : Comparison condition of AN002
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
CMPLCHA03 : Comparison condition of AN003
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
CMPLCHA05 : Comparison condition of AN005
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
CMPLCHA06 : Comparison condition of AN006
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
CMPLCHA07 : Comparison condition of AN007
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
A/D Compare Function Window A Comparison Condition Setting Register 1
address_offset : 0x9A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPLCHA16 : Comparison condition of AN016
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
CMPLCHA17 : Comparison condition of AN017
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
CMPLCHA18 : Comparison condition of AN018
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
CMPLCHA20 : Comparison condition of AN020
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
End of enumeration elements list.
A/D Compare Function Window A Lower-Side Level Setting Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPDR0 : The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A.
bits : 0 - 14 (15 bit)
access : read-write
A/D Compare Function Window A Upper-Side Level Setting Register
address_offset : 0x9E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPDR1 : The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.
bits : 0 - 14 (15 bit)
access : read-write
A/D-Converted Value Addition/Average Channel Select Register 1
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADS16 : A/D-Converted Value Addition/Average Channel AN016 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN016 is not selected.
#1 : 1
AN016 is selected.
End of enumeration elements list.
ADS17 : A/D-Converted Value Addition/Average Channel AN017 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN017 is not selected.
#1 : 1
AN017 is selected.
End of enumeration elements list.
ADS18 : A/D-Converted Value Addition/Average Channel AN018 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN018 is not selected.
#1 : 1
AN018 is selected.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
ADS20 : A/D-Converted Value Addition/Average Channel AN020 Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
AN020 is not selected.
#1 : 1
AN020 is selected.
End of enumeration elements list.
A/D Compare Function Window A Channel Status Register 0
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPSTCHA00 : Compare window A flag of AN000
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
CMPSTCHA01 : Compare window A flag of AN001
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
CMPSTCHA02 : Compare window A flag of AN002
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
CMPSTCHA03 : Compare window A flag of AN003
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
CMPSTCHA05 : Compare window A flag of AN005
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
CMPSTCHA06 : Compare window A flag of AN006
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
CMPSTCHA07 : Compare window A flag of AN007
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
A/D Compare Function Window A Channel Status Register 1
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPSTCHA16 : Compare window A flag of AN016
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
CMPSTCHA17 : Compare window A flag of AN017
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
CMPSTCHA18 : Compare window A flag of AN018
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
CMPSTCHA20 : Compare window A flag of AN020
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
A/D Compare Function Window A Extended Input Channel Status Register
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPSTTSA : Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
CMPSTOCA : Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 2 - 6 (5 bit)
access : read-write
A/D Compare Function Window B Channel Selection Register
address_offset : 0xA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPCHB : Compare window B channel selection bit. The channel that compares it on the condition of compare window B is selected.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0x00 : 0x00
AN000
0x01 : 0x01
AN001
0x02 : 0x02
AN002
0x03 : 0x03
AN003
0x05 : 0x05
AN005
0x06 : 0x06
AN006
0x07 : 0x07
AN007
0x10 : 0x10
AN016
0x11 : 0x11
AN017
0x12 : 0x12
AN018
0x14 : 0x14
AN020
0x20 : 0x20
Temperature sensor
0x21 : 0x21
Internal reference voltage
0x3F : 0x3F
No channel is selected
: others
Setting prohibited
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
CMPLB : Compare window B Compare condition setting bit.
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1)
#1 : 1
CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1)
End of enumeration elements list.
A/D Compare Function Window B Lower-Side Level Setting Register
address_offset : 0xA8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADWINLLB : This register is used to compare A window function is used to set the lower level of the window B.
bits : 0 - 14 (15 bit)
access : read-write
A/D Compare Function Window B Upper-Side Level Setting Register
address_offset : 0xAA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADWINULB : This register is used to compare A window function is used to set the higher level of the window B.
bits : 0 - 14 (15 bit)
access : read-write
A/D Compare Function Window B Status Register
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPSTB : Compare window B flag. It is a status flag that shows the comparative result of CH (AN000-AN003, AN005-AN007, AN016-AN018, AN020, temperature sensor, and internal reference voltage) made the object of window B relation condition.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Comparison conditions are not met.
#1 : 1
Comparison conditions are met.
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 1 - 6 (6 bit)
access : read-write
A/D-Converted Value Addition/Average Count Select Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC : Addition frequency selection bit. NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
1-time conversion (no addition same as normal conversion)
#001 : 001
2-time conversion (addition once)
#010 : 010
3-time conversion (addition twice)
#011 : 011
4-time conversion (addition three times)
#101 : 101
16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy.
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 3 - 5 (3 bit)
access : read-write
AVEE : Average mode enable bit. Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode.
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
A/D Sampling State Register L
address_offset : 0xDD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling Time Setting (AN016-AN018 and AN020)
bits : 0 - 6 (7 bit)
access : read-write
A/D Sampling State Register T
address_offset : 0xDE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling Time Setting (temperature sensor output)
bits : 0 - 6 (7 bit)
access : read-write
A/D Sampling State Register O
address_offset : 0xDF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling Time Setting (Internal reference voltage)
bits : 0 - 6 (7 bit)
access : read-write
A/D Control Extended Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved : This bit is read as 0. The write value should be 0.
bits : 0 - -1 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 0 - -1 (0 bit)
access : read-write
ADPRC : A/D Conversion Accuracy Specify
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : 00
A/D conversion is performed with 12-bit accuracy.
#01 : 01
A/D conversion is performed with 10-bit accuracy.
#10 : 10
A/D conversion is performed with 8-bit accuracy.
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 4 - 3 (0 bit)
access : read-write
ACE : A/D Data Register Automatic Clearing Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing.
#1 : 1
Enables automatic clearing.
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
DIAGVAL : Self-Diagnosis Conversion Voltage Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
When the self-diagnosis fixation mode is selected, it set prohibits it.
#01 : 01
The self-diagnosis by using the voltage of 0V.
#10 : 10
The self-diagnosis by using the voltage of reference supply x 1/2.
#11 : 11
The self-diagnosis by using the voltage of the reference supply.
End of enumeration elements list.
DIAGLD : Self-Diagnosis Mode Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Rotation mode for self-diagnosis voltage
#1 : 1
Fixed mode for self-diagnosis voltage
End of enumeration elements list.
DIAGM : Self-Diagnosis Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables self-diagnosis of ADC12.
#1 : 1
Enables self-diagnosis of ADC12.
End of enumeration elements list.
ADRFMT : A/D Data Register Format Select
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Flush-right is selected for the A/D data register format.
#1 : 1
Flush-left is selected for the A/D data register format.
End of enumeration elements list.
A/D Sampling State Register %s (Corresponding Channel is AN00)
address_offset : 0xE0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling time setting
bits : 0 - 6 (7 bit)
access : read-write
A/D Sampling State Register %s (Corresponding Channel is AN00)
address_offset : 0xE1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling time setting
bits : 0 - 6 (7 bit)
access : read-write
A/D Sampling State Register %s (Corresponding Channel is AN00)
address_offset : 0xE2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling time setting
bits : 0 - 6 (7 bit)
access : read-write
A/D Sampling State Register %s (Corresponding Channel is AN00)
address_offset : 0xE3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling time setting
bits : 0 - 6 (7 bit)
access : read-write
A/D Sampling State Register %s (Corresponding Channel is AN00)
address_offset : 0xE5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling time setting
bits : 0 - 6 (7 bit)
access : read-write
A/D Sampling State Register %s (Corresponding Channel is AN00)
address_offset : 0xE6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling time setting
bits : 0 - 6 (7 bit)
access : read-write
A/D Sampling State Register %s (Corresponding Channel is AN00)
address_offset : 0xE7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Sampling time setting
bits : 0 - 6 (7 bit)
access : read-write
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