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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x104 byte (0x0)
mem_usage : registers
protection :

Registers

IFSR

CCR0

DAR7

NPKT0

CPKT0

SAR0

DAR0

CCR1

NPKT1

CPKT1

SAR1

IFCR

DAR1

CCR2

NPKT2

CPKT2

SAR2

DAR2

CCR3

NPKT3

CPKT3

SAR3

CSR

DAR3

CCR4

NPKT4

CPKT4

SAR4

DAR4

CCR5

NPKT5

CPKT5

SAR5

DAR5

CCR6

NPKT6

CPKT6

SAR6

DAR6

CCR7

NPKT7

CPKT7

SAR7


IFSR

IFSR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IFSR IFSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BEIF TCIF HTIF TEIF

BEIF :
bits : 0 - 7 (8 bit)
access : read-only

TCIF :
bits : 8 - 23 (16 bit)
access : read-only

HTIF :
bits : 16 - 39 (24 bit)
access : read-only

TEIF :
bits : 24 - 55 (32 bit)
access : read-only


CCR0

CCR0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR0 CCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE BEIE TEIE rev1 DPTYP SPTYP DSIZE SSIZE PL BURSTLEN STRMSEL TRGMODE rev0

EN :
bits : 0 - 0 (1 bit)
access : read-write

TCIE :
bits : 1 - 2 (2 bit)
access : read-write

HTIE :
bits : 2 - 4 (3 bit)
access : read-write

BEIE :
bits : 3 - 6 (4 bit)
access : read-write

TEIE :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

DPTYP :
bits : 6 - 13 (8 bit)
access : read-write

SPTYP :
bits : 8 - 17 (10 bit)
access : read-write

DSIZE :
bits : 10 - 21 (12 bit)
access : read-write

SSIZE :
bits : 12 - 25 (14 bit)
access : read-write

PL :
bits : 14 - 29 (16 bit)
access : read-write

BURSTLEN :
bits : 16 - 35 (20 bit)
access : read-write

STRMSEL :
bits : 20 - 42 (23 bit)
access : read-write

TRGMODE :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


DAR7

DAR7
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR7 DAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NPKT0

NPKT0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPKT0 NPKT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPKT rev0

NPKT :
bits : 0 - 10 (11 bit)
access : read-write

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


CPKT0

CPKT0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPKT0 CPKT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPKT rev0

CPKT :
bits : 0 - 10 (11 bit)
access : read-only

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


SAR0

SAR0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR0 SAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAR0

DAR0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR0 DAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR1

CCR1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE BEIE TEIE rev1 DPTYP SPTYP DSIZE SSIZE PL BURSTLEN STRMSEL TRGMODE rev0

EN :
bits : 0 - 0 (1 bit)
access : read-write

TCIE :
bits : 1 - 2 (2 bit)
access : read-write

HTIE :
bits : 2 - 4 (3 bit)
access : read-write

BEIE :
bits : 3 - 6 (4 bit)
access : read-write

TEIE :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

DPTYP :
bits : 6 - 13 (8 bit)
access : read-write

SPTYP :
bits : 8 - 17 (10 bit)
access : read-write

DSIZE :
bits : 10 - 21 (12 bit)
access : read-write

SSIZE :
bits : 12 - 25 (14 bit)
access : read-write

PL :
bits : 14 - 29 (16 bit)
access : read-write

BURSTLEN :
bits : 16 - 35 (20 bit)
access : read-write

STRMSEL :
bits : 20 - 42 (23 bit)
access : read-write

TRGMODE :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


NPKT1

NPKT1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPKT1 NPKT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPKT rev0

NPKT :
bits : 0 - 10 (11 bit)
access : read-write

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


CPKT1

CPKT1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPKT1 CPKT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPKT rev0

CPKT :
bits : 0 - 10 (11 bit)
access : read-only

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


SAR1

SAR1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR1 SAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IFCR

IFCR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR IFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBEIF CTCIF CHTIF CTEIF

CBEIF :
bits : 0 - 7 (8 bit)
access : read-write

CTCIF :
bits : 8 - 23 (16 bit)
access : read-write

CHTIF :
bits : 16 - 39 (24 bit)
access : read-write

CTEIF :
bits : 24 - 55 (32 bit)
access : read-write


DAR1

DAR1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR1 DAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR2

CCR2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE BEIE TEIE rev1 DPTYP SPTYP DSIZE SSIZE PL BURSTLEN STRMSEL TRGMODE rev0

EN :
bits : 0 - 0 (1 bit)
access : read-write

TCIE :
bits : 1 - 2 (2 bit)
access : read-write

HTIE :
bits : 2 - 4 (3 bit)
access : read-write

BEIE :
bits : 3 - 6 (4 bit)
access : read-write

TEIE :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

DPTYP :
bits : 6 - 13 (8 bit)
access : read-write

SPTYP :
bits : 8 - 17 (10 bit)
access : read-write

DSIZE :
bits : 10 - 21 (12 bit)
access : read-write

SSIZE :
bits : 12 - 25 (14 bit)
access : read-write

PL :
bits : 14 - 29 (16 bit)
access : read-write

BURSTLEN :
bits : 16 - 35 (20 bit)
access : read-write

STRMSEL :
bits : 20 - 42 (23 bit)
access : read-write

TRGMODE :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


NPKT2

NPKT2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPKT2 NPKT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPKT rev0

NPKT :
bits : 0 - 10 (11 bit)
access : read-write

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


CPKT2

CPKT2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPKT2 CPKT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPKT rev0

CPKT :
bits : 0 - 10 (11 bit)
access : read-only

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


SAR2

SAR2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR2 SAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAR2

DAR2
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR2 DAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR3

CCR3
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR3 CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE BEIE TEIE rev1 DPTYP SPTYP DSIZE SSIZE PL BURSTLEN STRMSEL TRGMODE rev0

EN :
bits : 0 - 0 (1 bit)
access : read-write

TCIE :
bits : 1 - 2 (2 bit)
access : read-write

HTIE :
bits : 2 - 4 (3 bit)
access : read-write

BEIE :
bits : 3 - 6 (4 bit)
access : read-write

TEIE :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

DPTYP :
bits : 6 - 13 (8 bit)
access : read-write

SPTYP :
bits : 8 - 17 (10 bit)
access : read-write

DSIZE :
bits : 10 - 21 (12 bit)
access : read-write

SSIZE :
bits : 12 - 25 (14 bit)
access : read-write

PL :
bits : 14 - 29 (16 bit)
access : read-write

BURSTLEN :
bits : 16 - 35 (20 bit)
access : read-write

STRMSEL :
bits : 20 - 42 (23 bit)
access : read-write

TRGMODE :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


NPKT3

NPKT3
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPKT3 NPKT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPKT rev0

NPKT :
bits : 0 - 10 (11 bit)
access : read-write

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


CPKT3

CPKT3
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPKT3 CPKT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPKT rev0

CPKT :
bits : 0 - 10 (11 bit)
access : read-only

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


SAR3

SAR3
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR3 SAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CSR

CSR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRG DBUSY BURSTIDLE rev0 RELOAD

SWTRG :
bits : 0 - 7 (8 bit)
access : read-write

DBUSY :
bits : 8 - 23 (16 bit)
access : read-only

BURSTIDLE :
bits : 16 - 35 (20 bit)
access : read-write

rev0 :
bits : 20 - 43 (24 bit)
access : read-write

RELOAD :
bits : 24 - 55 (32 bit)
access : read-write


DAR3

DAR3
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR3 DAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR4

CCR4
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR4 CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE BEIE TEIE rev1 DPTYP SPTYP DSIZE SSIZE PL BURSTLEN STRMSEL TRGMODE rev0

EN :
bits : 0 - 0 (1 bit)
access : read-write

TCIE :
bits : 1 - 2 (2 bit)
access : read-write

HTIE :
bits : 2 - 4 (3 bit)
access : read-write

BEIE :
bits : 3 - 6 (4 bit)
access : read-write

TEIE :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

DPTYP :
bits : 6 - 13 (8 bit)
access : read-write

SPTYP :
bits : 8 - 17 (10 bit)
access : read-write

DSIZE :
bits : 10 - 21 (12 bit)
access : read-write

SSIZE :
bits : 12 - 25 (14 bit)
access : read-write

PL :
bits : 14 - 29 (16 bit)
access : read-write

BURSTLEN :
bits : 16 - 35 (20 bit)
access : read-write

STRMSEL :
bits : 20 - 42 (23 bit)
access : read-write

TRGMODE :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


NPKT4

NPKT4
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPKT4 NPKT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPKT rev0

NPKT :
bits : 0 - 10 (11 bit)
access : read-write

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


CPKT4

CPKT4
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPKT4 CPKT4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPKT rev0

CPKT :
bits : 0 - 10 (11 bit)
access : read-only

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


SAR4

SAR4
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR4 SAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAR4

DAR4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR4 DAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR5

CCR5
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR5 CCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE BEIE TEIE rev1 DPTYP SPTYP DSIZE SSIZE PL BURSTLEN STRMSEL TRGMODE rev0

EN :
bits : 0 - 0 (1 bit)
access : read-write

TCIE :
bits : 1 - 2 (2 bit)
access : read-write

HTIE :
bits : 2 - 4 (3 bit)
access : read-write

BEIE :
bits : 3 - 6 (4 bit)
access : read-write

TEIE :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

DPTYP :
bits : 6 - 13 (8 bit)
access : read-write

SPTYP :
bits : 8 - 17 (10 bit)
access : read-write

DSIZE :
bits : 10 - 21 (12 bit)
access : read-write

SSIZE :
bits : 12 - 25 (14 bit)
access : read-write

PL :
bits : 14 - 29 (16 bit)
access : read-write

BURSTLEN :
bits : 16 - 35 (20 bit)
access : read-write

STRMSEL :
bits : 20 - 42 (23 bit)
access : read-write

TRGMODE :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


NPKT5

NPKT5
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPKT5 NPKT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPKT rev0

NPKT :
bits : 0 - 10 (11 bit)
access : read-write

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


CPKT5

CPKT5
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPKT5 CPKT5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPKT rev0

CPKT :
bits : 0 - 10 (11 bit)
access : read-only

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


SAR5

SAR5
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR5 SAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAR5

DAR5
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR5 DAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR6

CCR6
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR6 CCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE BEIE TEIE rev1 DPTYP SPTYP DSIZE SSIZE PL BURSTLEN STRMSEL TRGMODE rev0

EN :
bits : 0 - 0 (1 bit)
access : read-write

TCIE :
bits : 1 - 2 (2 bit)
access : read-write

HTIE :
bits : 2 - 4 (3 bit)
access : read-write

BEIE :
bits : 3 - 6 (4 bit)
access : read-write

TEIE :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

DPTYP :
bits : 6 - 13 (8 bit)
access : read-write

SPTYP :
bits : 8 - 17 (10 bit)
access : read-write

DSIZE :
bits : 10 - 21 (12 bit)
access : read-write

SSIZE :
bits : 12 - 25 (14 bit)
access : read-write

PL :
bits : 14 - 29 (16 bit)
access : read-write

BURSTLEN :
bits : 16 - 35 (20 bit)
access : read-write

STRMSEL :
bits : 20 - 42 (23 bit)
access : read-write

TRGMODE :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


NPKT6

NPKT6
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPKT6 NPKT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPKT rev0

NPKT :
bits : 0 - 10 (11 bit)
access : read-write

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


CPKT6

CPKT6
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPKT6 CPKT6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPKT rev0

CPKT :
bits : 0 - 10 (11 bit)
access : read-only

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


SAR6

SAR6
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR6 SAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAR6

DAR6
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR6 DAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR7

CCR7
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR7 CCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE BEIE TEIE rev1 DPTYP SPTYP DSIZE SSIZE PL BURSTLEN STRMSEL TRGMODE rev0

EN :
bits : 0 - 0 (1 bit)
access : read-write

TCIE :
bits : 1 - 2 (2 bit)
access : read-write

HTIE :
bits : 2 - 4 (3 bit)
access : read-write

BEIE :
bits : 3 - 6 (4 bit)
access : read-write

TEIE :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

DPTYP :
bits : 6 - 13 (8 bit)
access : read-write

SPTYP :
bits : 8 - 17 (10 bit)
access : read-write

DSIZE :
bits : 10 - 21 (12 bit)
access : read-write

SSIZE :
bits : 12 - 25 (14 bit)
access : read-write

PL :
bits : 14 - 29 (16 bit)
access : read-write

BURSTLEN :
bits : 16 - 35 (20 bit)
access : read-write

STRMSEL :
bits : 20 - 42 (23 bit)
access : read-write

TRGMODE :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


NPKT7

NPKT7
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPKT7 NPKT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPKT rev0

NPKT :
bits : 0 - 10 (11 bit)
access : read-write

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


CPKT7

CPKT7
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPKT7 CPKT7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPKT rev0

CPKT :
bits : 0 - 10 (11 bit)
access : read-only

rev0 :
bits : 11 - 42 (32 bit)
access : read-write


SAR7

SAR7
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR7 SAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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