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UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

FR

ADDR

BRT

CR

TDR

RDR


FR

FR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR FR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RI TI TC TXCOL RXOV FE PE LBD rev2 RIC rev1 TCC TXCOLC RXOVC FEC PEC LBDC rev0

RI :
bits : 0 - 0 (1 bit)
access : read-only

TI :
bits : 1 - 2 (2 bit)
access : read-only

TC :
bits : 2 - 4 (3 bit)
access : read-only

TXCOL :
bits : 3 - 6 (4 bit)
access : read-only

RXOV :
bits : 4 - 8 (5 bit)
access : read-only

FE :
bits : 5 - 10 (6 bit)
access : read-only

PE :
bits : 6 - 12 (7 bit)
access : read-only

LBD :
bits : 7 - 14 (8 bit)
access : read-only

rev2 :
bits : 8 - 23 (16 bit)
access : read-write

RIC :
bits : 16 - 32 (17 bit)
access : read-write

rev1 :
bits : 17 - 34 (18 bit)
access : read-write

TCC :
bits : 18 - 36 (19 bit)
access : read-write

TXCOLC :
bits : 19 - 38 (20 bit)
access : read-write

RXOVC :
bits : 20 - 40 (21 bit)
access : read-write

FEC :
bits : 21 - 42 (22 bit)
access : read-write

PEC :
bits : 22 - 44 (23 bit)
access : read-write

LBDC :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write


ADDR

ADDR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADDR SMAR rev0

SADDR :
bits : 0 - 7 (8 bit)
access : read-write

SMAR :
bits : 8 - 23 (16 bit)
access : read-write

rev0 :
bits : 16 - 47 (32 bit)
access : read-write


BRT

BRT
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRT BRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBRT rev1 BFINE rev0

SBRT :
bits : 0 - 14 (15 bit)
access : read-write

rev1 :
bits : 15 - 30 (16 bit)
access : read-write

BFINE :
bits : 16 - 35 (20 bit)
access : read-write

rev0 :
bits : 20 - 51 (32 bit)
access : read-write


CR

CR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP SBRTEN SMOD RIE TIE TCIE LBDIE LBDL RB8 TB8 PS PCE SM2 SM SBK LINEN REN TEN DMAR DMAT rev0

STOP :
bits : 0 - 0 (1 bit)
access : read-write

SBRTEN :
bits : 1 - 2 (2 bit)
access : read-write

SMOD :
bits : 2 - 4 (3 bit)
access : read-write

RIE :
bits : 3 - 6 (4 bit)
access : read-write

TIE :
bits : 4 - 8 (5 bit)
access : read-write

TCIE :
bits : 5 - 10 (6 bit)
access : read-write

LBDIE :
bits : 6 - 12 (7 bit)
access : read-write

LBDL :
bits : 7 - 14 (8 bit)
access : read-write

RB8 :
bits : 8 - 16 (9 bit)
access : read-only

TB8 :
bits : 9 - 18 (10 bit)
access : read-write

PS :
bits : 10 - 20 (11 bit)
access : read-write

PCE :
bits : 11 - 22 (12 bit)
access : read-write

SM2 :
bits : 12 - 24 (13 bit)
access : read-write

SM :
bits : 13 - 27 (15 bit)
access : read-write

SBK :
bits : 15 - 30 (16 bit)
access : read-write

LINEN :
bits : 16 - 32 (17 bit)
access : read-write

REN :
bits : 17 - 34 (18 bit)
access : read-write

TEN :
bits : 18 - 36 (19 bit)
access : read-write

DMAR :
bits : 19 - 38 (20 bit)
access : read-write

DMAT :
bits : 20 - 40 (21 bit)
access : read-write

rev0 :
bits : 21 - 52 (32 bit)
access : read-write


TDR

TDR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR TDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDR rev0

TDR :
bits : 0 - 7 (8 bit)
access : read-write

rev0 :
bits : 8 - 39 (32 bit)
access : read-write


RDR

RDR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDR RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDR rev0

RDR :
bits : 0 - 7 (8 bit)
access : read-only

rev0 :
bits : 8 - 39 (32 bit)
access : read-write



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