CRC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

DR

CR

INIT


DR

DR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CR

CR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD rev1 MODE COMPLW RBITW RBYTEW COMPLR RBITR RBYTER rev0
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RELOAD :
bits : 0 - 0
access : read-write

rev1 :
bits : 1 - 8
access : read-write

MODE :
bits : 8 - 17
access : read-write

COMPLW :
bits : 10 - 20
access : read-write

RBITW :
bits : 11 - 22
access : read-write

RBYTEW :
bits : 12 - 24
access : read-write

COMPLR :
bits : 13 - 26
access : read-write

RBITR :
bits : 14 - 28
access : read-write

RBYTER :
bits : 15 - 30
access : read-write

rev0 :
bits : 16 - 47
access : read-write


INIT

INIT
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INIT INIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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