\n

IWDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

Registers

CR

CLR


CR

CR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTRLR IWDTPR IWDTON LOCK

IWDTRLR :
bits : 0 - 11 (12 bit)
access : read-write

IWDTPR :
bits : 12 - 26 (15 bit)
access : read-write

IWDTON :
bits : 15 - 30 (16 bit)
access : read-write

LOCK :
bits : 16 - 47 (32 bit)
access : read-write


CLR

CLR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CLR CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTCLR rev0

IWDTCLR :
bits : 0 - 15 (16 bit)
access : write-only

rev0 :
bits : 16 - 47 (32 bit)
access : write-only



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