\n

SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

Registers

PWRCR

DBGCR

PWRSR

SAFR

CRAMLOCK


PWRCR

PWRCR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRCR PWRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBOD BODMD BODIE BODEN rev0

VBOD :
bits : 0 - 3 (4 bit)
access : read-write

BODMD :
bits : 4 - 9 (6 bit)
access : read-write

BODIE :
bits : 6 - 12 (7 bit)
access : read-write

BODEN :
bits : 7 - 14 (8 bit)
access : read-write

rev0 :
bits : 8 - 39 (32 bit)
access : read-write


DBGCR

DBGCR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCR DBGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_SLEEP DBG_STOP rev0 DBG_DMA DBG_IWDT DBG_WWDT DBG_GPT DBG_TIM DBG_MCM DBG_UART DBG_SPI DBG_TWI LOCK

DBG_SLEEP :
bits : 0 - 0 (1 bit)
access : read-write

DBG_STOP :
bits : 1 - 2 (2 bit)
access : read-write

rev0 :
bits : 2 - 8 (7 bit)
access : read-write

DBG_DMA :
bits : 7 - 14 (8 bit)
access : read-write

DBG_IWDT :
bits : 8 - 16 (9 bit)
access : read-write

DBG_WWDT :
bits : 9 - 18 (10 bit)
access : read-write

DBG_GPT :
bits : 10 - 20 (11 bit)
access : read-write

DBG_TIM :
bits : 11 - 22 (12 bit)
access : read-write

DBG_MCM :
bits : 12 - 24 (13 bit)
access : read-write

DBG_UART :
bits : 13 - 26 (14 bit)
access : read-write

DBG_SPI :
bits : 14 - 28 (15 bit)
access : read-write

DBG_TWI :
bits : 15 - 30 (16 bit)
access : read-write

LOCK :
bits : 16 - 47 (32 bit)
access : read-write


PWRSR

PWRSR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRSR PWRSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODIF BODF rev0

BODIF :
bits : 0 - 0 (1 bit)
access : read-write

BODF :
bits : 1 - 2 (2 bit)
access : read-only

rev0 :
bits : 2 - 33 (32 bit)
access : read-write


SAFR

SAFR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAFR SAFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCCFG SWJCFG IEN_EXTI0 IEN_BOD IEN_CSM rev0 LOCK

OSCCFG :
bits : 0 - 1 (2 bit)
access : read-write

SWJCFG :
bits : 2 - 6 (5 bit)
access : read-write

IEN_EXTI0 :
bits : 5 - 10 (6 bit)
access : read-write

IEN_BOD :
bits : 6 - 12 (7 bit)
access : read-write

IEN_CSM :
bits : 7 - 14 (8 bit)
access : read-write

rev0 :
bits : 8 - 23 (16 bit)
access : read-write

LOCK :
bits : 16 - 47 (32 bit)
access : read-write


CRAMLOCK

CRAMLOCK
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRAMLOCK CRAMLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRAMLCK rev0 LOCK

CRAMLCK :
bits : 0 - 7 (8 bit)
access : read-write

rev0 :
bits : 8 - 23 (16 bit)
access : read-write

LOCK :
bits : 16 - 47 (32 bit)
access : read-write



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