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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection :

Registers

CR

CICLR

AHBRSTR

APB2RSTR

APB1RSTR

AHBENR

APB2ENR

APB1ENR

RSTSTR

RSTCLR

HSICAL

RCCLOCK

CFGR

CIENR

CISTR


CR

CR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HSEON HSERDY PLLON PLLRDY rev0

SW :
bits : 0 - 1 (2 bit)
access : read-write

SWS :
bits : 2 - 5 (4 bit)
access : read-only

HSEON :
bits : 4 - 8 (5 bit)
access : read-write

HSERDY :
bits : 5 - 10 (6 bit)
access : read-only

PLLON :
bits : 6 - 12 (7 bit)
access : read-write

PLLRDY :
bits : 7 - 14 (8 bit)
access : read-only

rev0 :
bits : 8 - 39 (32 bit)
access : read-write


CICLR

CICLR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CICLR CICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rev2 HSERDYC PLLRDYC rev1 CSMC rev0

rev2 :
bits : 0 - 2 (3 bit)
access : read-write

HSERDYC :
bits : 3 - 6 (4 bit)
access : read-write

PLLRDYC :
bits : 4 - 8 (5 bit)
access : read-write

rev1 :
bits : 5 - 11 (7 bit)
access : read-write

CSMC :
bits : 7 - 14 (8 bit)
access : read-write

rev0 :
bits : 8 - 39 (32 bit)
access : read-write


AHBRSTR

AHBRSTR
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBRSTR AHBRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOCFGRST IODATRST rev1 ADC1RST ADC2RST ADC3RST SYSCFGRST DMARST MACPRST CRCRST GPT0RST GPT1RST GPT2RST GPT3RST GPTRST rev0

IOCFGRST :
bits : 0 - 0 (1 bit)
access : read-write

IODATRST :
bits : 1 - 2 (2 bit)
access : read-write

rev1 :
bits : 2 - 4 (3 bit)
access : read-write

ADC1RST :
bits : 3 - 6 (4 bit)
access : read-write

ADC2RST :
bits : 4 - 8 (5 bit)
access : read-write

ADC3RST :
bits : 5 - 10 (6 bit)
access : read-write

SYSCFGRST :
bits : 6 - 12 (7 bit)
access : read-write

DMARST :
bits : 7 - 14 (8 bit)
access : read-write

MACPRST :
bits : 8 - 16 (9 bit)
access : read-write

CRCRST :
bits : 9 - 18 (10 bit)
access : read-write

GPT0RST :
bits : 10 - 20 (11 bit)
access : read-write

GPT1RST :
bits : 11 - 22 (12 bit)
access : read-write

GPT2RST :
bits : 12 - 24 (13 bit)
access : read-write

GPT3RST :
bits : 13 - 26 (14 bit)
access : read-write

GPTRST :
bits : 14 - 28 (15 bit)
access : read-write

rev0 :
bits : 15 - 46 (32 bit)
access : read-write


APB2RSTR

APB2RSTR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM1RST MCM2RST rev0

MCM1RST :
bits : 0 - 0 (1 bit)
access : read-write

MCM2RST :
bits : 1 - 2 (2 bit)
access : read-write

rev0 :
bits : 2 - 33 (32 bit)
access : read-write


APB1RSTR

APB1RSTR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR APB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM5RST TIM6RST TIM7RST TIM8RST QEIRST UART1RST UART2RST UART3RST SPI1RST SPI2RST rev1 TWI1RST WWDTRST AMOCRST rev0

TIM5RST :
bits : 0 - 0 (1 bit)
access : read-write

TIM6RST :
bits : 1 - 2 (2 bit)
access : read-write

TIM7RST :
bits : 2 - 4 (3 bit)
access : read-write

TIM8RST :
bits : 3 - 6 (4 bit)
access : read-write

QEIRST :
bits : 4 - 8 (5 bit)
access : read-write

UART1RST :
bits : 5 - 10 (6 bit)
access : read-write

UART2RST :
bits : 6 - 12 (7 bit)
access : read-write

UART3RST :
bits : 7 - 14 (8 bit)
access : read-write

SPI1RST :
bits : 8 - 16 (9 bit)
access : read-write

SPI2RST :
bits : 9 - 18 (10 bit)
access : read-write

rev1 :
bits : 10 - 20 (11 bit)
access : read-write

TWI1RST :
bits : 11 - 22 (12 bit)
access : read-write

WWDTRST :
bits : 12 - 24 (13 bit)
access : read-write

AMOCRST :
bits : 13 - 26 (14 bit)
access : read-write

rev0 :
bits : 14 - 45 (32 bit)
access : read-write


AHBENR

AHBENR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBENR AHBENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOCFGEN IODATEN rev1 ADC1EN ADC2EN ADC3EN SYSCFGEN DMAEN MACPEN CRCEN GPT0EN GPT1EN GPT2EN GPT3EN GPTEN rev0

IOCFGEN :
bits : 0 - 0 (1 bit)
access : read-write

IODATEN :
bits : 1 - 2 (2 bit)
access : read-write

rev1 :
bits : 2 - 4 (3 bit)
access : read-write

ADC1EN :
bits : 3 - 6 (4 bit)
access : read-write

ADC2EN :
bits : 4 - 8 (5 bit)
access : read-write

ADC3EN :
bits : 5 - 10 (6 bit)
access : read-write

SYSCFGEN :
bits : 6 - 12 (7 bit)
access : read-write

DMAEN :
bits : 7 - 14 (8 bit)
access : read-write

MACPEN :
bits : 8 - 16 (9 bit)
access : read-write

CRCEN :
bits : 9 - 18 (10 bit)
access : read-write

GPT0EN :
bits : 10 - 20 (11 bit)
access : read-write

GPT1EN :
bits : 11 - 22 (12 bit)
access : read-write

GPT2EN :
bits : 12 - 24 (13 bit)
access : read-write

GPT3EN :
bits : 13 - 26 (14 bit)
access : read-write

GPTEN :
bits : 14 - 28 (15 bit)
access : read-write

rev0 :
bits : 15 - 46 (32 bit)
access : read-write


APB2ENR

APB2ENR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM1EN MCM2EN rev0

MCM1EN :
bits : 0 - 0 (1 bit)
access : read-write

MCM2EN :
bits : 1 - 2 (2 bit)
access : read-write

rev0 :
bits : 2 - 33 (32 bit)
access : read-write


APB1ENR

APB1ENR
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR APB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM5EN TIM6EN TIM7EN TIM8EN QEIEN UART1EN UART2EN UART3EN SPI1EN SPI2EN rev1 TWI1EN WWDTEN AMOCEN rev0

TIM5EN :
bits : 0 - 0 (1 bit)
access : read-write

TIM6EN :
bits : 1 - 2 (2 bit)
access : read-write

TIM7EN :
bits : 2 - 4 (3 bit)
access : read-write

TIM8EN :
bits : 3 - 6 (4 bit)
access : read-write

QEIEN :
bits : 4 - 8 (5 bit)
access : read-write

UART1EN :
bits : 5 - 10 (6 bit)
access : read-write

UART2EN :
bits : 6 - 12 (7 bit)
access : read-write

UART3EN :
bits : 7 - 14 (8 bit)
access : read-write

SPI1EN :
bits : 8 - 16 (9 bit)
access : read-write

SPI2EN :
bits : 9 - 18 (10 bit)
access : read-write

rev1 :
bits : 10 - 20 (11 bit)
access : read-write

TWI1EN :
bits : 11 - 22 (12 bit)
access : read-write

WWDTEN :
bits : 12 - 24 (13 bit)
access : read-write

AMOCEN :
bits : 13 - 26 (14 bit)
access : read-write

rev0 :
bits : 14 - 45 (32 bit)
access : read-write


RSTSTR

RSTSTR
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSTSTR RSTSTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINRSTF LVRSTF PORSTF SWRSTF IWDTRSTF WWDTRSTF LVRSTF2 rev0

PINRSTF :
bits : 0 - 0 (1 bit)
access : read-only

LVRSTF :
bits : 1 - 2 (2 bit)
access : read-only

PORSTF :
bits : 2 - 4 (3 bit)
access : read-only

SWRSTF :
bits : 3 - 6 (4 bit)
access : read-only

IWDTRSTF :
bits : 4 - 8 (5 bit)
access : read-only

WWDTRSTF :
bits : 5 - 10 (6 bit)
access : read-only

LVRSTF2 :
bits : 6 - 12 (7 bit)
access : read-only

rev0 :
bits : 7 - 38 (32 bit)
access : read-write


RSTCLR

RSTCLR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCLR RSTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINRSTFC LVRSTFC PORSTFC SWRSTFC IWDTRSTFC WWDTRSTFC LVRSTF2C rev0

PINRSTFC :
bits : 0 - 0 (1 bit)
access : read-write

LVRSTFC :
bits : 1 - 2 (2 bit)
access : read-write

PORSTFC :
bits : 2 - 4 (3 bit)
access : read-write

SWRSTFC :
bits : 3 - 6 (4 bit)
access : read-write

IWDTRSTFC :
bits : 4 - 8 (5 bit)
access : read-write

WWDTRSTFC :
bits : 5 - 10 (6 bit)
access : read-write

LVRSTF2C :
bits : 6 - 12 (7 bit)
access : read-write

rev0 :
bits : 7 - 38 (32 bit)
access : read-write


HSICAL

HSICAL
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSICAL HSICAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSITRIM rev1 HSICAL TRIMREF rev0 TRIMRUN

HSITRIM :
bits : 0 - 2 (3 bit)
access : read-write

rev1 :
bits : 3 - 10 (8 bit)
access : read-write

HSICAL :
bits : 8 - 23 (16 bit)
access : read-only

TRIMREF :
bits : 16 - 44 (29 bit)
access : read-only

rev0 :
bits : 29 - 59 (31 bit)
access : read-write

TRIMRUN :
bits : 31 - 62 (32 bit)
access : read-write


RCCLOCK

RCCLOCK
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCCLOCK RCCLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK rev0

LOCK :
bits : 0 - 15 (16 bit)
access : read-write

rev0 :
bits : 16 - 47 (32 bit)
access : read-write


CFGR

CFGR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRE PPRE1 PPRE2 PLLK PLLF PLLSRC PLLXTPRE rev0

HPRE :
bits : 0 - 2 (3 bit)
access : read-write

PPRE1 :
bits : 3 - 8 (6 bit)
access : read-write

PPRE2 :
bits : 6 - 14 (9 bit)
access : read-write

PLLK :
bits : 9 - 20 (12 bit)
access : read-write

PLLF :
bits : 12 - 29 (18 bit)
access : read-write

PLLSRC :
bits : 18 - 36 (19 bit)
access : read-write

PLLXTPRE :
bits : 19 - 38 (20 bit)
access : read-write

rev0 :
bits : 20 - 51 (32 bit)
access : read-write


CIENR

CIENR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIENR CIENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rev1 HSERDYIE PLLRDYIE rev0

rev1 :
bits : 0 - 2 (3 bit)
access : read-write

HSERDYIE :
bits : 3 - 6 (4 bit)
access : read-write

PLLRDYIE :
bits : 4 - 8 (5 bit)
access : read-write

rev0 :
bits : 5 - 36 (32 bit)
access : read-write


CISTR

CISTR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CISTR CISTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rev2 HSERDYIF PLLRDYIF rev1 CSMHSEF CSMPLLF rev0

rev2 :
bits : 0 - 2 (3 bit)
access : read-write

HSERDYIF :
bits : 3 - 6 (4 bit)
access : read-only

PLLRDYIF :
bits : 4 - 8 (5 bit)
access : read-only

rev1 :
bits : 5 - 10 (6 bit)
access : read-write

CSMHSEF :
bits : 6 - 12 (7 bit)
access : read-only

CSMPLLF :
bits : 7 - 14 (8 bit)
access : read-only

rev0 :
bits : 8 - 39 (32 bit)
access : read-write



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