\n

FLASH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x214 byte (0x0)
mem_usage : registers
protection :

Registers

ACR

CR

MEMRMP

OPR

RPR

OPR_CUST1

OPR_DESI0

OPR_DESI1

OPR_DESI2

OPR_DESI3

WRPR

CNTR

UPCNTR

CNTCR

MKYR

IKYR

E2KYR

SR


ACR

ACR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY rev1 PRFTEN ICEN DCEN CRST rev0 LOCK

LATENCY :
bits : 0 - 2 (3 bit)
access : read-write

rev1 :
bits : 3 - 10 (8 bit)
access : read-write

PRFTEN :
bits : 8 - 16 (9 bit)
access : read-write

ICEN :
bits : 9 - 18 (10 bit)
access : read-write

DCEN :
bits : 10 - 20 (11 bit)
access : read-write

CRST :
bits : 11 - 22 (12 bit)
access : read-write

rev0 :
bits : 12 - 27 (16 bit)
access : read-write

LOCK :
bits : 16 - 47 (32 bit)
access : read-write


CR

CR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNB rev2 STRT rev1 PSIZE INFLCK rev0 E2LCK MNLCK CMD

SNB :
bits : 0 - 6 (7 bit)
access : read-write

rev2 :
bits : 7 - 14 (8 bit)
access : read-write

STRT :
bits : 8 - 16 (9 bit)
access : read-write

rev1 :
bits : 9 - 19 (11 bit)
access : read-write

PSIZE :
bits : 11 - 22 (12 bit)
access : read-write

INFLCK :
bits : 12 - 24 (13 bit)
access : read-write

rev0 :
bits : 13 - 26 (14 bit)
access : read-write

E2LCK :
bits : 14 - 28 (15 bit)
access : read-write

MNLCK :
bits : 15 - 30 (16 bit)
access : read-write

CMD :
bits : 16 - 47 (32 bit)
access : read-write


MEMRMP

MEMRMP
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMRMP MEMRMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMMODE rev0

MEMMODE :
bits : 0 - 15 (16 bit)
access : read-write

rev0 :
bits : 16 - 47 (32 bit)
access : read-write


OPR

OPR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPR OPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPT0 OPT1 OPT2 OPT3

OPT0 :
bits : 0 - 7 (8 bit)
access : read-write

OPT1 :
bits : 8 - 23 (16 bit)
access : read-write

OPT2 :
bits : 16 - 39 (24 bit)
access : read-write

OPT3 :
bits : 24 - 55 (32 bit)
access : read-write


RPR

RPR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RPR RPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDP rev0

RDP :
bits : 0 - 15 (16 bit)
access : read-only

rev0 :
bits : 16 - 47 (32 bit)
access : read-write


OPR_CUST1

OPR_CUST1
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPR_CUST1 OPR_CUST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPT0 OPT1 OPT2 OPT3

OPT0 :
bits : 0 - 7 (8 bit)
access : read-write

OPT1 :
bits : 8 - 23 (16 bit)
access : read-write

OPT2 :
bits : 16 - 39 (24 bit)
access : read-write

OPT3 :
bits : 24 - 55 (32 bit)
access : read-write


OPR_DESI0

OPR_DESI0
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPR_DESI0 OPR_DESI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPT0 OPT1 OPT2 OPT3

OPT0 :
bits : 0 - 7 (8 bit)
access : read-write

OPT1 :
bits : 8 - 23 (16 bit)
access : read-write

OPT2 :
bits : 16 - 39 (24 bit)
access : read-write

OPT3 :
bits : 24 - 55 (32 bit)
access : read-write


OPR_DESI1

OPR_DESI1
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPR_DESI1 OPR_DESI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPT0 OPT1 OPT2 OPT3

OPT0 :
bits : 0 - 7 (8 bit)
access : read-write

OPT1 :
bits : 8 - 23 (16 bit)
access : read-write

OPT2 :
bits : 16 - 39 (24 bit)
access : read-write

OPT3 :
bits : 24 - 55 (32 bit)
access : read-write


OPR_DESI2

OPR_DESI2
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPR_DESI2 OPR_DESI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPT0 OPT1 OPT2 OPT3

OPT0 :
bits : 0 - 7 (8 bit)
access : read-write

OPT1 :
bits : 8 - 23 (16 bit)
access : read-write

OPT2 :
bits : 16 - 39 (24 bit)
access : read-write

OPT3 :
bits : 24 - 55 (32 bit)
access : read-write


OPR_DESI3

OPR_DESI3
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPR_DESI3 OPR_DESI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPT0 OPT1 OPT2 OPT3

OPT0 :
bits : 0 - 7 (8 bit)
access : read-write

OPT1 :
bits : 8 - 23 (16 bit)
access : read-write

OPT2 :
bits : 16 - 39 (24 bit)
access : read-write

OPT3 :
bits : 24 - 55 (32 bit)
access : read-write


WRPR

WRPR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WRPR WRPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CNTR

CNTR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

UPCNTR

UPCNTR
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCNTR UPCNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CNTCR

CNTCR
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTCR CNTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN rev0

CNTEN :
bits : 0 - 0 (1 bit)
access : read-write

rev0 :
bits : 1 - 32 (32 bit)
access : read-write


MKYR

MKYR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MKYR MKYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IKYR

IKYR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IKYR IKYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

E2KYR

E2KYR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

E2KYR E2KYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SR

SR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOP OPERR rev3 FLSERR WRPRTERR PGPERR PGWERR STAERR rev2 BSY EOPC OPERRC rev1 FLSERRC WRPRTERRC PGPERRC PGWERRC STAERRC rev0

EOP :
bits : 0 - 0 (1 bit)
access : read-only

OPERR :
bits : 1 - 2 (2 bit)
access : read-only

rev3 :
bits : 2 - 4 (3 bit)
access : read-write

FLSERR :
bits : 3 - 6 (4 bit)
access : read-only

WRPRTERR :
bits : 4 - 8 (5 bit)
access : read-only

PGPERR :
bits : 5 - 10 (6 bit)
access : read-only

PGWERR :
bits : 6 - 12 (7 bit)
access : read-only

STAERR :
bits : 7 - 14 (8 bit)
access : read-only

rev2 :
bits : 8 - 22 (15 bit)
access : read-write

BSY :
bits : 15 - 30 (16 bit)
access : read-only

EOPC :
bits : 16 - 32 (17 bit)
access : read-write

OPERRC :
bits : 17 - 34 (18 bit)
access : read-write

rev1 :
bits : 18 - 36 (19 bit)
access : read-write

FLSERRC :
bits : 19 - 38 (20 bit)
access : read-write

WRPRTERRC :
bits : 20 - 40 (21 bit)
access : read-write

PGPERRC :
bits : 21 - 42 (22 bit)
access : read-write

PGWERRC :
bits : 22 - 44 (23 bit)
access : read-write

STAERRC :
bits : 23 - 46 (24 bit)
access : read-write

rev0 :
bits : 24 - 55 (32 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.