\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
ADDR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMADR :
bits : 0 - 13 (14 bit)
access : read-write
rev1 :
bits : 14 - 41 (28 bit)
access : read-write
RAMTYP :
bits : 28 - 57 (30 bit)
access : read-write
rev0 :
bits : 30 - 61 (32 bit)
access : read-write
CFG
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKSZ :
bits : 0 - 2 (3 bit)
access : read-write
rev1 :
bits : 3 - 17 (15 bit)
access : read-write
SEL :
bits : 15 - 30 (16 bit)
access : read-write
rev0 :
bits : 16 - 47 (32 bit)
access : read-write
CSR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUN :
bits : 0 - 15 (16 bit)
access : read-write
MOD :
bits : 16 - 32 (17 bit)
access : read-write
BSY :
bits : 17 - 34 (18 bit)
access : read-only
ERR :
bits : 18 - 36 (19 bit)
access : read-write
rev0 :
bits : 19 - 50 (32 bit)
access : read-write
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