\n

RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

IC

SECCNTV

SECCNT

ALMCNTV

ALMCNT

CLKS

IE

RIS


CTRL

Offset:0x00 RTC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTCEN

RTCEN : RTC enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable RTC

1 : Enable

Enable RTC

End of enumeration elements list.


IC

Offset:0x10 RTC Interrupt Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IC IC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECIC ALMIC OVFIC

SECIC : Second interrupt flag clear
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear second interrupt flag

End of enumeration elements list.

ALMIC : Alarm interrupt flag clear
bits : 1 - 2 (2 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear alarm interrupt flag

End of enumeration elements list.

OVFIC : Overflow interrupt flag clear
bits : 2 - 4 (3 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear overflow interrupt flag

End of enumeration elements list.


SECCNTV

Offset:0x14 RTC Second Counter Reload Value Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECCNTV SECCNTV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SECCNT

Offset:0x18 RTC Second Counter Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SECCNT SECCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ALMCNTV

Offset:0x1C RTC Alarm Counter Reload Value Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMCNTV ALMCNTV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ALMCNT

Offset:0x20 RTC Alarm Counter Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ALMCNT ALMCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLKS

Offset:0x04 RTC Clock Source Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKS CLKS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL

CLKSEL : RTC clock source
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : ILRC

ILRC is RTC clock source

1 : ELS XTAL

ELS Xtal is RTC clock source

3 : EHS XTAL clock/128

EHS Xtal/128 is RTC clock source

End of enumeration elements list.


IE

Offset:0x08 RTC Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECIE ALMIE OVFIE

SECIE : Second interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable second interrupt

1 : Enable

Enable second interrupt

End of enumeration elements list.

ALMIE : Alarm interrupt enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable alarm interrupt

1 : Enable

Enable alarm interrupt

End of enumeration elements list.

OVFIE : Overflow interrupt enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

Disable overflow interrupt

1 : Enable

Enable overflow interrupt

End of enumeration elements list.


RIS

Offset:0x0C RTC Raw Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECIF ALMIF OVFIF

SECIF : Second interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : No

No second interrupt

1 : Met second interrupt requirements

Second interrupt is triggered when SECIE=1

End of enumeration elements list.

ALMIF : Alarm interrupt flag
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0 : No

No alarm interrupt

1 : Met alarm interrupt requirements

Alarm interrupt is triggered when ALMIE=1

End of enumeration elements list.

OVFIF : Overflow interrupt flag
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

0 : No

No overflow interrupt

1 : Met overflow interrupt requirements

Overflow interrupt is triggered when OVFIE=1

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.