\n
address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :
Offset:0x00 PMU Backup Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x10 PMU Backup Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x14 PMU Backup Register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x18 PMU Backup Register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x1C PMU Backup Register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x20 PMU Backup Register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x24 PMU Backup Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x28 PMU Backup Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x2C PMU Backup Register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x30 PMU Backup Register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x34 PMU Backup Register 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x38 PMU Backup Register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x3C PMU Backup Register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x04 PMU Backup Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x40 PMU Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Low Power mode selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : Disable
Disable Low-power mode
2 : Deep-sleep mode
WFI instruction will make MCU enter Deep-sleep mode
4 : Sleep mode
WFI instruction will make MCU enter Sleep mode
End of enumeration elements list.
Offset:0x44 PMU Latch Control Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LATCHEN : Latch enable bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Enable GPIO latch function
End of enumeration elements list.
LATCHKEY : Latch register key
bits : 16 - 47 (32 bit)
access : write-only
Offset:0x48 PMU Latch Control Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LATCHDIS : Latch disable bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Disable GPIO latch function
End of enumeration elements list.
LATCHKEY : Latch register key
bits : 16 - 47 (32 bit)
access : write-only
Offset:0x4C PMU Latch Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LATCHST : Latch status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Not latched
GPIO is Not latched
1 : Latched
GPIO status is latched
End of enumeration elements list.
Offset:0x08 PMU Backup Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x0C PMU Backup Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKUPDATA : Data retained
bits : 0 - 7 (8 bit)
access : read-write
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