SYSTEM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

ANBCTRL

AHBCP

RSTST

LVDCTRL

EXRSTCTRL

SWDCTRL

IVTM

NDTCTRL

NDTSTS

IHRCADJ

PLLCTRL

CSST

CLKCFG


ANBCTRL

Offset:0x00 Analog Block Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IHRCEN ELSEN EHSEN EHSFREQ

IHRCEN : IHRC enable
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable IHRC

1 : Enable

Enable IHRC

End of enumeration elements list.

ELSEN : ELS XTAL enable
bits : 2 - 4
access : read-write

Enumeration:

0 : Disable

Disable ELS Xtal

1 : Enable

Enable ELS Xtal

End of enumeration elements list.

EHSEN : EHS XTAL enable
bits : 4 - 8
access : read-write

Enumeration:

0 : Disable

Disable EHS Xtal

1 : Enable

Enable EHS Xtal

End of enumeration elements list.

EHSFREQ : EHS XTAL frequency range
bits : 5 - 10
access : read-write

Enumeration:

0 : Low

Less equal than 12MHz

1 : High

Greater than 12MHz

End of enumeration elements list.


AHBCP

Offset:0x10 AHB Clock Prescale Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBPRE DIV1P5

AHBPRE : AHB clock source prescaler
bits : 0 - 2
access : read-write

Enumeration:

0 : 000b

FAHB=FSYSCLK/1

1 : 001b

FAHB=FSYSCLK/2

2 : 010b

FAHB=FSYSCLK/4

3 : 011b

FAHB=FSYSCLK/8

4 : 100b

FAHB=FSYSCLK/16

5 : 101b

FAHB=FSYSCLK/32

6 : 110b

FAHB=FSYSCLK/64

7 : 111b

FAHB=FSYSCLK/128

End of enumeration elements list.

DIV1P5 : SYSCLK prescaler
bits : 3 - 6
access : read-write

Enumeration:

0 : DIV1

SYSCLK = SYSCLK/1

1 : DIV1P5

SYSCLK = SYSCLK/1.5

End of enumeration elements list.


RSTST

Offset:0x14 System Reset Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRSTF WDTRSTF LVDRSTF EXTRSTF PORRSTF

SWRSTF : Software reset flag
bits : 0 - 0
access : read-write

Enumeration:

0 : 0

No SW reset occurred

1 : 1

SW reset occurred

End of enumeration elements list.

WDTRSTF : WDT reset flag
bits : 1 - 2
access : read-write

Enumeration:

0 : 0

No WDT reset occurred

1 : 1

WDT reset occurred

End of enumeration elements list.

LVDRSTF : LVD reset flag
bits : 2 - 4
access : read-write

Enumeration:

0 : 0

No LVD reset occurred

1 : 1

LVD reset occurred

End of enumeration elements list.

EXTRSTF : External reset flag
bits : 3 - 6
access : read-write

Enumeration:

0 : 0

No Extenral reset occurred

1 : 1

External reset occurred

End of enumeration elements list.

PORRSTF : POR reset flag
bits : 4 - 8
access : read-write

Enumeration:

0 : 0

No POR occurred

1 : 1

POR occurred

End of enumeration elements list.


LVDCTRL

Offset:0x18 LVD Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDRSTLVL LVDINTLVL LVDRSTEN LVDEN

LVDRSTLVL : LVD reset level
bits : 0 - 2
access : read-write

Enumeration:

3 : 2.70V

LVD reset threshold is 2.70V

4 : 3.00V

LVD reset threshold is 3.00V

5 : 3.60V

LVD reset threshold is 3.60V

End of enumeration elements list.

LVDINTLVL : LVD interrupt level
bits : 4 - 10
access : read-write

Enumeration:

3 : 2.70V

LVD interrupt threshold is 2.70V

4 : 3.00V

LVD interrupt threshold is 3.00V

5 : 3.60V

LVD interrupt threshold is 3.60V

End of enumeration elements list.

LVDRSTEN : LVD Reset enable
bits : 14 - 28
access : read-write

Enumeration:

0 : Diable

Disable LVD reset

1 : Enable

Enable LVD reset

End of enumeration elements list.

LVDEN : LVD enable
bits : 15 - 30
access : read-write

Enumeration:

0 : Diable

Disable LVD

1 : Enable

Enable LVD

End of enumeration elements list.


EXRSTCTRL

Offset:0x1C External Reset Pin Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESETDIS

RESETDIS : External reset pin disable
bits : 0 - 0
access : read-write

Enumeration:

0 : Enable

P3.7 acts as nRESET pin

1 : Disable

P3.7 acts as GPIO pin

End of enumeration elements list.


SWDCTRL

Offset:0x20 SWD Pin Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWDDIS

SWDDIS : SWD pin disable
bits : 0 - 0
access : read-write

Enumeration:

0 : Enable

Enable SWD pins

1 : Disable

Disable SWD pins

End of enumeration elements list.


IVTM

Offset:0x24 Interrupt Vector Table Mapping register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IVTM IVTMKEY
Warning: Undefined array key 48 in /app/public/svg.inc on line 285

IVTM : Interrupt table mapping selection
bits : 0 - 2
access : read-write

Enumeration:

0 : 000b

Map to Boot ROM

1 : 001b

Map to User ROM 1

2 : 010b

Map to SRAM

3 : 011b

Map to User ROM 2

4 : 100b

Map to User ROM 3

5 : 101b

Map to User ROM 4

End of enumeration elements list.

IVTMKEY : IVTM register key
bits : 16 - 47
access : write-only

Enumeration:

End of enumeration elements list.


NDTCTRL

Offset:0x28 Noise Detect Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT5V_IE

NDT5V_IE : NDT for VDD 5V interrupt enable bit
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

Disable NDT5V interrupt

1 : Enable

Enable NDT5V interrupt

End of enumeration elements list.


NDTSTS

Offset:0x2C Noise Detect Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT5V_DET

NDT5V_DET : Power noise status of NDT5V
bits : 1 - 2
access : read-write

Enumeration:

0 : No

No power noise is detected

1 : Detected

Power noise is detected by NDT5V IP

End of enumeration elements list.


IHRCADJ

Offset:0x34 IHRC Frequency Adjustment register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADJEN DIR ADJ SYSKEY
Warning: Undefined array key 48 in /app/public/svg.inc on line 285

ADJEN : IHRC frequency adjustment enable bit
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable IHRC frequency adjustment

1 : Enable

Enable IHRC frequency adjustment

End of enumeration elements list.

DIR : IHRC frequency adjusting direction bit
bits : 1 - 2
access : read-write

Enumeration:

0 : Positive

Positive direction

1 : Negative

Negative direction

End of enumeration elements list.

ADJ : IHRC frequency adjusting bits
bits : 4 - 15
access : read-write

SYSKEY : System register key
bits : 16 - 47
access : write-only


PLLCTRL

Offset:0x04 PLL Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEL PSEL PLLCLKSEL PLLEN

MSEL : M value
bits : 0 - 2
access : read-write

Enumeration:

0 : 000b

M=4

1 : 001b

M=6

2 : 010b

M=8

3 : 011b

M=10

4 : 100b

M=12

End of enumeration elements list.

PSEL : P value
bits : 5 - 10
access : read-write

Enumeration:

0 : 2

P=2

1 : 4

P=4

End of enumeration elements list.

PLLCLKSEL : PLL clock source
bits : 12 - 24
access : read-write

Enumeration:

0 : IHRC

12MHz

1 : EHS XTAL

10MHz~25MHz

End of enumeration elements list.

PLLEN : PLL enable
bits : 15 - 30
access : read-write

Enumeration:

0 : Disable

Disable PLL

1 : Enable

Enable PLL

End of enumeration elements list.


CSST

Offset:0x08 Clock Source Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IHRCRDY ELSRDY EHSRDY PLLRDY

IHRCRDY : IHRC ready flag
bits : 0 - 0
access : read-only

Enumeration:

0 : Not Ready

IHRC is Not Ready

1 : Ready

IHRC is Ready

End of enumeration elements list.

ELSRDY : ELS XTAL ready flag
bits : 2 - 4
access : read-only

Enumeration:

0 : Not Ready

ELS Xtal is Not Ready

1 : Ready

ELS Xtal is Ready

End of enumeration elements list.

EHSRDY : EHS XTAL ready flag
bits : 4 - 8
access : read-only

Enumeration:

0 : Not Ready

EHS Xtal is Not Ready

1 : Ready

EHS Xtal is Ready

End of enumeration elements list.

PLLRDY : PLL ready flag
bits : 6 - 12
access : read-only

Enumeration:

0 : Not Locked

PLL is Not locked

1 : Locked

PLL is locked

End of enumeration elements list.


CLKCFG

Offset:0x0C System Clock Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCLKSEL SYSCLKST

SYSCLKSEL : System clock source selection
bits : 0 - 2
access : read-write

Enumeration:

0 : IHRC

HCLK=IHRC

1 : ILRC

HCLK=ILRC

2 : EHS XTAL

HCLK=EHS XTAL

3 : ELS XTAL

HCLK=ELS XTAL

4 : PLL Output

HCLK=PLL output

End of enumeration elements list.

SYSCLKST : System clock switch status
bits : 4 - 10
access : read-only

Enumeration:

0 : IHRC

IHRC is used as system clock

1 : ILRC

ILRC is used as system clock

2 : EHS XTAL

EHS XTAL is used as system clock

3 : ELS XTAL

ELS XTAL is used as system clock

4 : PLL

PLL output is used as system clock

End of enumeration elements list.



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