CMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

IE

RIS

IC

DB

CSCTRL

CSCTRL1

CSCNT

CTRL1

VIREF

OS


CTRL

Offset:0x00 CMP Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0EN CM0PS CM0NS CM0RS CM0OEN CM0G CM1EN
Warning: Undefined array key 33 in /app/public/svg.inc on line 285
CM1PS
Warning: Undefined array key 36 in /app/public/svg.inc on line 285
CM1NS
Warning: Undefined array key 40 in /app/public/svg.inc on line 285
CM1RS
Warning: Undefined array key 47 in /app/public/svg.inc on line 285
CM1OEN
Warning: Undefined array key 54 in /app/public/svg.inc on line 285
CM1G
Warning: Undefined array key 57 in /app/public/svg.inc on line 285

CM0EN : CMP0 Enable bit
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable CMP0

1 : Enable

Enable CMP0

End of enumeration elements list.

CM0PS : CMP0 Positive input selection bits
bits : 1 - 3
access : read-write

Enumeration:

0 : No

CM0P0/CM0P1/CM0P2 pins are GPIO mode

1 : CM0P0

CM0P0 is positive input pin

2 : CM0P1

CM0P1 is positive input pin

3 : CM0P2

CM0P2 is positive input pin

End of enumeration elements list.

CM0NS : CMP0 Negative input pin
bits : 3 - 7
access : read-write

Enumeration:

0 : CM0N0

CM0N0 is negative input pin

1 : CM0N1

CM0N1 is negative input pin

2 : CM0N2

CM0N2 is negative input pin

3 : VIREF0

CM0N0/CM0N1/CM0N2 pins are GPIO mode

End of enumeration elements list.

CM0RS : CMP0 internal reference voltage (VIREF0) selection bits
bits : 5 - 14
access : read-write

Enumeration:

0 : 00000b

VIREF0=VIREF

1 : 00001b

VIREF0=VIREF*1/32

2 : 00010b

VIREF0=VIREF*2/32

3 : 00011b

VIREF0=VIREF*3/32

4 : 00100b

VIREF0=VIREF*4/32

5 : 00101b

VIREF0=VIREF*5/32

6 : 00110b

VIREF0=VIREF*6/32

7 : 00111b

VIREF0=VIREF*7/32

8 : 01000b

VIREF0=VIREF*8/32

9 : 01001b

VIREF0=VIREF*9/32

10 : 01010b

VIREF0=VIREF*10/32

11 : 01011b

VIREF0=VIREF*11/32

12 : 01100b

VIREF0=VIREF*12/32

13 : 01101b

VIREF0=VIREF*13/32

14 : 01110b

VIREF0=VIREF*14/32

15 : 01111b

VIREF0=VIREF*15/32

16 : 10000b

VIREF0=VIREF*16/32

17 : 10001b

VIREF0=VIREF*17/32

18 : 10010b

VIREF0=VIREF*18/32

19 : 10011b

VIREF0=VIREF*19/32

20 : 10100b

VIREF0=VIREF*20/32

21 : 10101b

VIREF0=VIREF*21/32

22 : 10110b

VIREF0=VIREF*22/32

23 : 10111b

VIREF0=VIREF*23/32

24 : 11000b

VIREF0=VIREF*24/32

25 : 11001b

VIREF0=VIREF*25/32

26 : 11010b

VIREF0=VIREF*26/32

27 : 11011b

VIREF0=VIREF*27/32

28 : 11100b

VIREF0=VIREF*28/32

29 : 11101b

VIREF0=VIREF*29/32

30 : 11110b

VIREF0=VIREF*30/32

31 : 11111b

VIREF0=VIREF*31/32

End of enumeration elements list.

CM0OEN : CMP0 Output pin control bits
bits : 10 - 21
access : read-write

Enumeration:

0 : Disable

Disable CM0O

1 : P2.0

P2.0 is CM0O and isolate GPIO function

2 : P2.6

P2.6 is CM0O and isolate GPIO function

3 : P3.3

P3.3 is CM0O and isolate GPIO function

End of enumeration elements list.

CM0G : CMP0 interrupt trigger direction control bit
bits : 12 - 24
access : read-write

Enumeration:

0 : Falling range trigger

CMP0 output status is from high to low as VPREF0 less than CM0N

1 : Rising edge trigger

CMP0 output status is from low to high as VPREF0 more than CM0N

End of enumeration elements list.

CM1EN : CMP1 Enable bit
bits : 16 - 32
access : read-write

Enumeration:

0 : Disable

Disable CMP1

1 : Enable

Enable CMP1

End of enumeration elements list.

CM1PS : CMP1 Positive input selection bits
bits : 17 - 35
access : read-write

Enumeration:

0 : No

CM1P0/CM1P1/CM1P2 pins are GPIO mode

1 : CM1P0

CM1P0 is positive input pin

2 : CM1P1

CM1P1 is positive input pin

3 : CM1P2

CM1P2 is positive input pin

End of enumeration elements list.

CM1NS : CMP1 Negative input pin
bits : 19 - 39
access : read-write

Enumeration:

0 : CM1N0

CM1N0

1 : CM1N1

CM1N1

2 : CM1N2

CM1N2

3 : VIREF1

CM1N0/CM1N1/CM1N2 pins are GPIO mode

End of enumeration elements list.

CM1RS : CMP1 internal reference voltage (VIREF1) selection bits
bits : 21 - 46
access : read-write

Enumeration:

0 : 00000b

VIREF1=VIREF

1 : 00001b

VIREF1=VIREF*1/32

2 : 00010b

VIREF1=VIREF*2/32

3 : 00011b

VIREF1=VIREF*3/32

4 : 00100b

VIREF1=VIREF*4/32

5 : 00101b

VIREF1=VIREF*5/32

6 : 00110b

VIREF1=VIREF*6/32

7 : 00111b

VIREF1=VIREF*7/32

8 : 01000b

VIREF1=VIREF*8/32

9 : 01001b

VIREF1=VIREF*9/32

10 : 01010b

VIREF1=VIREF*10/32

11 : 01011b

VIREF1=VIREF*11/32

12 : 01100b

VIREF1=VIREF*12/32

13 : 01101b

VIREF1=VIREF*13/32

14 : 01110b

VIREF1=VIREF*14/32

15 : 01111b

VIREF1=VIREF*15/32

16 : 10000b

VIREF1=VIREF*16/32

17 : 10001b

VIREF1=VIREF*17/32

18 : 10010b

VIREF1=VIREF*18/32

19 : 10011b

VIREF1=VIREF*19/32

20 : 10100b

VIREF1=VIREF*20/32

21 : 10101b

VIREF1=VIREF*21/32

22 : 10110b

VIREF1=VIREF*22/32

23 : 10111b

VIREF1=VIREF*23/32

24 : 11000b

VIREF1=VIREF*24/32

25 : 11001b

VIREF0=VIREF*25/32

26 : 11010b

VIREF1=VIREF*26/32

27 : 11011b

VIREF1=VIREF*27/32

28 : 11100b

VIREF1=VIREF*28/32

29 : 11101b

VIREF1=VIREF*29/32

30 : 11110b

VIREF1=VIREF*30/32

31 : 11111b

VIREF1=VIREF*31/32

End of enumeration elements list.

CM1OEN : CMP1 Output pin control bits
bits : 26 - 53
access : read-write

Enumeration:

0 : Disable

Disable CM1O

1 : P2.2

P2.2 is CM1O and isolate GPIO function

2 : P2.7

P2.7 is CM1O and isolate GPIO function

3 : P3.4

P3.4 is CM1O and isolate GPIO function

End of enumeration elements list.

CM1G : CMP1 interrupt trigger direction control bit
bits : 28 - 56
access : read-write

Enumeration:

0 : Falling range trigger

CMP1 output status is from high to low as VPREF1 less than CM1N

1 : Rising edge trigger

CMP1 output status is from low to high as VPREF1 more than CM1N

End of enumeration elements list.


IE

Offset:0x10 CMP Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IE CM1IE CM2IE CSIE

CM0IE : CMP0 interrupt enable
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable CMP0 interrupt

1 : Enable

Enable CMP0 interrupt

End of enumeration elements list.

CM1IE : CMP1 interrupt enable
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

Disable CMP1 interrupt

1 : Enable

Enable CMP1 interrupt

End of enumeration elements list.

CM2IE : CMP2 interrupt enable
bits : 2 - 4
access : read-write

Enumeration:

0 : Disable

Disable CMP2 interrupt

1 : Enable

Enable CMP2 interrupt

End of enumeration elements list.

CSIE : Cap-sensing interrupt enable
bits : 3 - 6
access : read-write

Enumeration:

0 : Disable

Disable CS interrupt

1 : Enable

Enable CS interrupt

End of enumeration elements list.


RIS

Offset:0x14 CMP n Raw Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IF CM1IF CM2IF CSIF

CM0IF : CMP0 raw interrupt flag
bits : 0 - 0
access : read-only

Enumeration:

0 : No interrupt

No interrupt on CMP0

1 : Met interrupt requirements

Interrupt requirements met on CMP0

End of enumeration elements list.

CM1IF : CMP1 raw interrupt flag
bits : 1 - 2
access : read-only

Enumeration:

0 : No interrupt

No interrupt on CMP1

1 : Met interrupt requirements

Interrupt requirements met on CMP1

End of enumeration elements list.

CM2IF : CMP2 raw interrupt flag
bits : 2 - 4
access : read-only

Enumeration:

0 : No interrupt

No interrupt on CMP2

1 : Met interrupt requirements

Interrupt requirements met on CMP2

End of enumeration elements list.

CSIF : Cap-sensing raw interrupt flag
bits : 3 - 6
access : read-only

Enumeration:

0 : No interrupt

No interrupt on Cap-sensing function

1 : Met interrupt requirements

Interrupt requirements met on Cap-sensing function

End of enumeration elements list.


IC

Offset:0x18 CMP Interrupt Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IC CM1IC CM2IC CSIC

CM0IC : CMP0 interrupt flag clear bit
bits : 0 - 0
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CMP0 interrupt flag

End of enumeration elements list.

CM1IC : CMP1 interrupt flag clear bit
bits : 1 - 2
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CMP1 interrupt flag

End of enumeration elements list.

CM2IC : CMP2 interrupt flag clear bit
bits : 2 - 4
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CMP2 interrupt flag

End of enumeration elements list.

CSIC : Cap-sensing interrupt flag clear bit
bits : 3 - 6
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CS interrupt flag

End of enumeration elements list.


DB

Offset:0x1C CMP Interrupt Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0DB CM1DB CM2DB CSDB

CM0DB : Count for CMP0 output debounce time
bits : 0 - 2
access : read-write

Enumeration:

0 : 000b

No CMP0 output debounce time

1 : 001b

CMP0 output debounce time=2*CMP0_PCLK

2 : 010b

CMP0 output debounce time=4*CMP0_PCLK

3 : 011b

CMP0 output debounce time=8*CMP0_PCLK

4 : 100b

CMP0 output debounce time=16*CMP0_PCLK

5 : 101b

CMP0 output debounce time=32*CMP0_PCLK

6 : 110b

CMP0 output debounce time=64*CMP0_PCLK

7 : 111b

CMP0 output debounce time=128*CMP0_PCLK

End of enumeration elements list.

CM1DB : Count for CMP1 output debounce time
bits : 4 - 10
access : read-write

Enumeration:

0 : 000b

No CMP1 output debounce time

1 : 001b

CMP1 output debounce time=2*CMP1_PCLK

2 : 010b

CMP1 output debounce time=4*CMP1_PCLK

3 : 011b

CMP1 output debounce time=8*CMP1_PCLK

4 : 100b

CMP1 output debounce time=16*CMP1_PCLK

5 : 101b

CMP1 output debounce time=32*CMP1_PCLK

6 : 110b

CMP1 output debounce time=64*CMP1_PCLK

7 : 111b

CMP1 output debounce time=128*CMP1_PCLK

End of enumeration elements list.

CM2DB : Count for CMP2 output debounce time
bits : 8 - 18
access : read-write

Enumeration:

0 : 000b

No CMP2 output debounce time

1 : 001b

CMP2 output debounce time=2*CMP2_PCLK

2 : 010b

CMP2 output debounce time=4*CMP2_PCLK

3 : 011b

CMP2 output debounce time=8*CMP2_PCLK

4 : 100b

CMP2 output debounce time=16*CMP2_PCLK

5 : 101b

CMP2 output debounce time=32*CMP2_PCLK

6 : 110b

CMP2 output debounce time=64*CMP2_PCLK

7 : 111b

CMP2 output debounce time=128*CMP2_PCLK

End of enumeration elements list.

CSDB : Count for Cap-sensing output debounce time
bits : 12 - 28
access : read-write

Enumeration:

0 : 00000b

No Cap-sening output debounce time

1 : 00001b

Cap-sensing output debounce time=1*CS_PCLK

2 : 00010b

Cap-sensing output debounce time=2*CS_PCLK

3 : 00011b

Cap-sensing output debounce time=3*CS_PCLK

4 : 00100b

Cap-sensing output debounce time=4*CS_PCLK

5 : 00101b

Cap-sensing output debounce time=5*CS_PCLK

6 : 00110b

Cap-sensing output debounce time=6*CS_PCLK

7 : 00111b

Cap-sensing output debounce time=7*CS_PCLK

8 : 01000b

Cap-sensing output debounce time=8*CS_PCLK

9 : 01001b

Cap-sensing output debounce time=9*CS_PCLK

10 : 01010b

Cap-sensing output debounce time=10*CS_PCLK

11 : 01011b

Cap-sensing output debounce time=11*CS_PCLK

12 : 01100b

Cap-sensing output debounce time=12*CS_PCLK

13 : 01101b

Cap-sensing output debounce time=13*CS_PCLK

14 : 01110b

Cap-sensing output debounce time=14*CS_PCLK

15 : 01111b

Cap-sensing output debounce time=15*CS_PCLK

16 : 10000b

Cap-sensing output debounce time=16*CS_PCLK

17 : 10001b

Cap-sensing output debounce time=17*CS_PCLK

18 : 10010b

Cap-sensing output debounce time=18*CS_PCLK

19 : 10011b

Cap-sensing output debounce time=19*CS_PCLK

20 : 10100b

Cap-sensing output debounce time=20*CS_PCLK

21 : 10101b

Cap-sensing output debounce time=21*CS_PCLK

22 : 10110b

Cap-sensing output debounce time=22*CS_PCLK

23 : 10111b

Cap-sensing output debounce time=23*CS_PCLK

24 : 11000b

Cap-sensing output debounce time=24*CS_PCLK

25 : 11001b

Cap-sensing output debounce time=25*CS_PCLK

26 : 11010b

Cap-sensing output debounce time=26*CS_PCLK

27 : 11011b

Cap-sensing output debounce time=27*CS_PCLK

28 : 11100b

Cap-sensing output debounce time=28*CS_PCLK

29 : 11101b

Cap-sensing output debounce time=29*CS_PCLK

30 : 11110b

Cap-sensing output debounce time=30*CS_PCLK

31 : 11111b

Cap-sensing output debounce time=31*CS_PCLK

End of enumeration elements list.


CSCTRL

Offset:0x20 CMP Cap-sensing Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSEN CSS CS1ST CSH CMP VDSEL CHG
Warning: Undefined array key 33 in /app/public/svg.inc on line 285
TNON
Warning: Undefined array key 38 in /app/public/svg.inc on line 285
CCAL
Warning: Undefined array key 44 in /app/public/svg.inc on line 285
CCAL4
Warning: Undefined array key 49 in /app/public/svg.inc on line 285
CSOUTEN
Warning: Undefined array key 51 in /app/public/svg.inc on line 285
CSDIS
Warning: Undefined array key 53 in /app/public/svg.inc on line 285
CSFAPC
Warning: Undefined array key 61 in /app/public/svg.inc on line 285
CSRDY
Warning: Undefined array key 63 in /app/public/svg.inc on line 285

CSEN : Cap-sensing module enable bit
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable CS module

1 : Enable

Enable CS module

End of enumeration elements list.

CSS : Cap-sensing operation start bit
bits : 1 - 2
access : read-write

Enumeration:

0 : Stop

Cap-sensing operation stops

1 : Start

Cap-sensing operation starts

End of enumeration elements list.

CS1ST : Cap-sensing channel scan group start bit
bits : 2 - 4
access : read-write

Enumeration:

0 : Not New

Not group scan start

1 : New

New group scan start

End of enumeration elements list.

CSH : Cap-sensing channel
bits : 3 - 10
access : read-write

Enumeration:

0 : 00000b

CT0

1 : 00001b

CT1

2 : 00010b

CT2

3 : 00011b

CT3

4 : 00100b

CT4

5 : 00101b

CT5

6 : 00110b

CT6

7 : 00111b

CT7

8 : 01000b

CT8

9 : 01001b

CT9

10 : 01010b

CT10

11 : 01011b

CT11

12 : 01100b

CT12

13 : 01101b

CT13

14 : 01110b

CT14

15 : 01111b

CT15

16 : 10000b

CT16

17 : 10001b

CT17

18 : 10010b

CT18

19 : 10011b

CT19

20 : 10100b

CT20

21 : 10101b

CT21

22 : 10110b

CT22

23 : 10111b

CT23

24 : 11000b

CT24 (Internal reference channel)

End of enumeration elements list.

CMP : Comparator reference control bits
bits : 11 - 24
access : read-write

Enumeration:

0 : 000b

0.3083*VREG33

1 : 001b

0.3583*VREG33

2 : 010b

0.3917*VREG33

3 : 011b

0.4417*VREG33

4 : 100b

0.5083*VREG33

5 : 101b

0.5583*VREG33

6 : 110b

0.5917*VREG33

7 : 111b

0.6417*VREG33

End of enumeration elements list.

VDSEL : Cap-sensing voltage detects select bit
bits : 14 - 28
access : read-write

Enumeration:

0 : Reserved

Reserved

1 : Comparator

Cap-sensing voltage is detected by Comparator

End of enumeration elements list.

CHG : Cap-sensing charging time
bits : 15 - 32
access : read-write

Enumeration:

0 : 000b

2us

1 : 001b

4us

2 : 010b

8us

3 : 011b

16us

4 : 100b

32us

5 : 101b

64us

6 : 110b

128us

7 : 111b

256us

End of enumeration elements list.

TNON : Non-overlap time
bits : 18 - 37
access : read-write

Enumeration:

0 : 0

13ns

1 : 1

26ns

2 : 2

39ns

3 : 3

52ns

End of enumeration elements list.

CCAL : Cap Calibration parameter
bits : 20 - 43
access : read-write

Enumeration:

0 : 0000b

0pF

1 : 0001b

0.2pF

2 : 0010b

0.4pF

3 : 0011b

0.6pF

4 : 0100b

0.8pF

5 : 0101b

1.0pF

6 : 0110b

1.2pF

7 : 0111b

1.4pF

8 : 1000b

1.6pF

9 : 1001b

1.8pF

10 : 1010b

2.0pF

11 : 1011b

2.2pF

12 : 1100b

2.4pF

13 : 1101b

2.6pF

14 : 1110b

2.8pF

15 : 1111b

3.0pF

End of enumeration elements list.

CCAL4 : Cap Calibration select bit
bits : 24 - 48
access : read-write

Enumeration:

0 : VSS

Cap Calibration circuit is connect to VSS

1 : VDD

Cap Calibration circuit is connect to VDD

End of enumeration elements list.

CSOUTEN : Cap-sening output pin enable bit
bits : 25 - 50
access : read-write

Enumeration:

0 : Disable

CSOUT pin is GPIO

1 : Enable

CSOUT pin is Cap-sensing output pin

End of enumeration elements list.

CSDIS : Channel discharge signl (CK_TCH) controll bit
bits : 26 - 52
access : read-write

Enumeration:

0 : Enable

Enable

1 : Disable

Disable

End of enumeration elements list.

CSFAPC : CSF active controll
bits : 30 - 60
access : read-write

Enumeration:

0 : Disable

CSF can be triggered any time

1 : Enable

CSF can be triggered while CSS is high.

End of enumeration elements list.

CSRDY : Cap-sensing module ready flag
bits : 31 - 62
access : read-only

Enumeration:

0 : Not Ready

Cap-sensing module are not ready

1 : Ready

Cap-sensing module are ready

End of enumeration elements list.


CSCTRL1

Offset:0x24 CMP Cap-sensing Control Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGFRQ SGSEL OSCR CSVCOV CSCOV

SGFRQ : Spread Spectrum frequency
bits : 0 - 1
access : read-write

Enumeration:

0 : 00b

4MHz

1 : 01b

2MHz

2 : 10b

1MHz

3 : 11b

0.5MHz

End of enumeration elements list.

SGSEL : Cap-sensing 4MHz clock source and SSCG select bit
bits : 6 - 13
access : read-write

Enumeration:

0 : 00b

4MHz IHRC and disable PRBS function

2 : 10b

4MHz Ring OSC. and disable PRBS function

End of enumeration elements list.

OSCR : Ring OSC.4MHz clock range
bits : 8 - 20
access : read-write

Enumeration:

0 : 00000b

4.096MHz

1 : 00001b

3.973MHz

2 : 00010b

3.973MHz

3 : 00011b

3.857MHz

4 : 00100b

3.414MHz

5 : 00101b

3.329MHz

6 : 00110b

3.330MHz

7 : 00111b

3.250MHz

8 : 01000b

4.564MHz

9 : 01001b

4.428MHz

10 : 01010b

4.427MHz

11 : 01011b

4.299MHz

12 : 01100b

3.808MHz

13 : 01101b

3.714MHz

14 : 01110b

3.715MHz

15 : 01111b

3.626MHz

16 : 10000b

5.157MHz

17 : 10001b

5.004MHz

18 : 10010b

5.004MHz

19 : 10011b

4.860MHz

20 : 10100b

4.308MHz

21 : 10101b

4.203MHz

22 : 10110b

4.203MHz

23 : 10111b

4.103MHz

24 : 11000b

6.416MHz

25 : 11001b

6.227MHz

26 : 11010b

6.227MHz

27 : 11011b

6.051MHz

28 : 11100b

5.372MHz

29 : 11101b

5.243MHz

30 : 11110b

5.243MHz

31 : 11111b

5.120MHz

End of enumeration elements list.

CSVCOV : CSV 16-bit event counter overflow indicator (Clock source is Cap-sensing 4MHz)
bits : 13 - 26
access : read-write

Enumeration:

0 : No

No overflow

1 : Overflow

CSV[15:0] event counter overflows

End of enumeration elements list.

CSCOV : CSC 16-bit timer counter overflow indicator (Clock source is CS_PCLK)
bits : 14 - 28
access : read-write

Enumeration:

0 : No

No overflow

1 : Overflow

CSC[15:0] timer counter overflows

End of enumeration elements list.


CSCNT

Offset:0x28 CMP CapSensing Counter Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSV CSC
Warning: Undefined array key 48 in /app/public/svg.inc on line 285

CSV : CSV 16-bit event counter (CSV counter clock source is CS_4MHz)
bits : 0 - 15
access : read-only

CSC : CSC 16-bit timer counter (CSC counter clock source is CS_PCLK)
bits : 16 - 47
access : read-only


CTRL1

Offset:0x04 CMP Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM2EN CM2PS CM2NS CM2RS CM2OEN CM2G

CM2EN : CMP2 Enable bit
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable CMP2

1 : Enable

Enable CMP2

End of enumeration elements list.

CM2PS : CMP2 Positive input selection bits
bits : 1 - 3
access : read-write

Enumeration:

0 : No

CM2P0/CM2P1/CM2P2 pins are GPIO mode

1 : CM2P0

CM2P0 is positive input pin

2 : CM2P1

CM2P1 is positive input pin

3 : CM2P2

CM2P2 is positive input pin

End of enumeration elements list.

CM2NS : CMP2 Negative input pin
bits : 3 - 7
access : read-write

Enumeration:

0 : CM2N0

CM2N0

1 : CM2N1

CM2N1

2 : CM2N2

CM2N2

3 : VIREF2

CM2N0/CM2N1/CM2N2 pins are GPIO mode

End of enumeration elements list.

CM2RS : CMP2 internal reference voltage (VIREF2) selection bits
bits : 5 - 14
access : read-write

Enumeration:

0 : 00000b

VIREF2=VIREF

1 : 00001b

VIREF2=VIREF*1/32

2 : 00010b

VIREF2=VIREF*2/32

3 : 00011b

VIREF2=VIREF*3/32

4 : 00100b

VIREF2=VIREF*4/32

5 : 00101b

VIREF2=VIREF*5/32

6 : 00110b

VIREF2=VIREF*6/32

7 : 00111b

VIREF2=VIREF*7/32

8 : 01000b

VIREF2=VIREF*8/32

9 : 01001b

VIREF2=VIREF*9/32

10 : 01010b

VIREF2=VIREF*10/32

11 : 01011b

VIREF2=VIREF*11/32

12 : 01100b

VIREF2=VIREF*12/32

13 : 01101b

VIREF2=VIREF*13/32

14 : 01110b

VIREF2=VIREF*14/32

15 : 01111b

VIREF2=VIREF*15/32

16 : 10000b

VIREF2=VIREF*16/32

17 : 10001b

VIREF2=VIREF*17/32

18 : 10010b

VIREF2=VIREF*18/32

19 : 10011b

VIREF2=VIREF*19/32

20 : 10100b

VIREF2=VIREF*20/32

21 : 10101b

VIREF2=VIREF*21/32

22 : 10110b

VIREF2=VIREF*22/32

23 : 10111b

VIREF2=VIREF*23/32

24 : 11000b

VIREF2=VIREF*24/32

25 : 11001b

VIREF2=VIREF*25/32

26 : 11010b

VIREF2=VIREF*26/32

27 : 11011b

VIREF2=VIREF*27/32

28 : 11100b

VIREF2=VIREF*28/32

29 : 11101b

VIREF2=VIREF*29/32

30 : 11110b

VIREF2=VIREF*30/32

31 : 11111b

VIREF2=VIREF*31/32

End of enumeration elements list.

CM2OEN : CMP2 Output pin control bits
bits : 10 - 21
access : read-write

Enumeration:

0 : Disable

Disable CM2O

1 : P0.12

P0.12 is CM2O and isolate GPIO function

2 : P0.3

P0.3 is CM2O and isolate GPIO function

3 : P3.8

P3.8 is CM2O and isolate GPIO function

End of enumeration elements list.

CM2G : CMP2 interrupt trigger direction control bit
bits : 12 - 24
access : read-write

Enumeration:

0 : Falling range trigger

CMP2 output status is from high to low as VPREF2 less than CM2N

1 : Rising edge trigger

CMP2 output status is from low to high as VPREF2 more than CM2N

End of enumeration elements list.


VIREF

Offset:0x08 CMP Internal Reference Voltage register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPIREFEN CMPIREF

CMPIREFEN : CMP internal reference voltage (VIREF) enable
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable CMP internal reference voltage

1 : Enable

Enable CMP internal reference voltage

End of enumeration elements list.

CMPIREF : CMP internal reference voltage (VIREF) source
bits : 1 - 3
access : read-write

Enumeration:

0 : VDD

VIREF=VDD

1 : Internal 1P5V

VIREF=Internal 1P5V

2 : Internal 2V

VIREF=Internal 2V

3 : Internal 3V

VIREF=Internal 3V

End of enumeration elements list.


OS

Offset:0xC CMP Output Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0OUT CM1OUT CM2OUT

CM0OUT : CMP0 Output flag bit
bits : 0 - 0
access : read-only

Enumeration:

0 : CMP0 V+ is less than V-

V0+ is less than V0-

1 : CMP0 V+ is more than V-

V0+ is more than V0-

End of enumeration elements list.

CM1OUT : CMP1 Output flag bit
bits : 1 - 2
access : read-only

Enumeration:

0 : CMP1 V+ is less than V-

V1+ is less than V1-

1 : CMP1 V+ is more than V-

V1+ is more than V1- voltage

End of enumeration elements list.

CM2OUT : CMP2 Output flag bit
bits : 2 - 4
access : read-only

Enumeration:

0 : CMP2 V+ is less than V-

V2+ is less than V2- voltage

1 : CMP2 V+ is more than V-

V2+ is more than V2- voltage

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.