TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

TMRCTRL

CNTCTRL

MCTRL

MCTRL2

MR0

MR1

MR2

MR3

MR4

MR5

MR6

MR7

TC

MR8

MR9

MR10

MR11

MR12

PRE

CAPCTRL

CAP0

EM

EMC

PWMCTRL

PWMENB

PWMIOENB

RIS

IC

PC


TMRCTRL

Offset:0x00 CT16Bn Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CRST CLKSEL

CEN : Counter enable
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable counter

1 : Enable

Enable Timer Counter and Prescale Counter for counting

End of enumeration elements list.

CRST : Counter Reset
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

Disable

1 : Reset Counter

Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK

End of enumeration elements list.

CLKSEL : PCLK source
bits : 2 - 4
access : read-write

Enumeration:

0 : HCLK

CT16Bn PCLK source=HCLK

1 : PLL_VCO

CT16Bn PCLK source=PLL_VCO

End of enumeration elements list.


CNTCTRL

Offset:0x10 CT16Bn Counter Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTM

CTM : Counter/Timer Mode
bits : 0 - 1
access : read-write

Enumeration:

0 : Timer Mode

Timer Mode: every rising PCLK edge

1 : Counter Mode 1

TC is incremented on rising edges on the CAP0 input selected by CIS bits.

2 : Counter Mode 2

TC is incremented on falling edges on the CAP0 input selected by CIS bits.

3 : Counter Mode 3

TC is incremented on both edges on the CAP0 input selected by CIS bits.

End of enumeration elements list.


MCTRL

Offset:0x14 CT16Bn Match Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IE MR0RST MR0STOP MR1IE MR1RST MR1STOP MR2IE MR2RST MR2STOP MR3IE MR3RST MR3STOP MR4IE MR4RST MR4STOP MR5IE MR5RST
Warning: Undefined array key 33 in /app/public/svg.inc on line 285
MR5STOP
Warning: Undefined array key 35 in /app/public/svg.inc on line 285
MR6IE
Warning: Undefined array key 37 in /app/public/svg.inc on line 285
MR6RST
Warning: Undefined array key 39 in /app/public/svg.inc on line 285
MR6STOP
Warning: Undefined array key 41 in /app/public/svg.inc on line 285
MR7IE
Warning: Undefined array key 43 in /app/public/svg.inc on line 285
MR7RST
Warning: Undefined array key 45 in /app/public/svg.inc on line 285
MR7STOP
Warning: Undefined array key 47 in /app/public/svg.inc on line 285
MR8IE
Warning: Undefined array key 49 in /app/public/svg.inc on line 285
MR8RST
Warning: Undefined array key 51 in /app/public/svg.inc on line 285
MR8STOP
Warning: Undefined array key 53 in /app/public/svg.inc on line 285
MR9IE
Warning: Undefined array key 55 in /app/public/svg.inc on line 285
MR9RST
Warning: Undefined array key 57 in /app/public/svg.inc on line 285
MR9STOP
Warning: Undefined array key 59 in /app/public/svg.inc on line 285

MR0IE : Enable generating an interrupt when MR0 matches TC
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR0 matches TC

End of enumeration elements list.

MR0RST : Enable reset TC when MR0 matches TC
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR0 matches TC

End of enumeration elements list.

MR0STOP : Stop TC and PC and clear CEN bit when MR0 matches TC
bits : 2 - 4
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR0 matches TC

End of enumeration elements list.

MR1IE : Enable generating an interrupt when MR1 matches TC
bits : 3 - 6
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR1 matches TC

End of enumeration elements list.

MR1RST : Enable reset TC when MR1 matches TC
bits : 4 - 8
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR1 matches TC

End of enumeration elements list.

MR1STOP : Stop TC and PC and clear CEN bit when MR1 matches TC
bits : 5 - 10
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR1 matches TC

End of enumeration elements list.

MR2IE : Enable generating an interrupt when MR2 matches TC
bits : 6 - 12
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR2 matches TC

End of enumeration elements list.

MR2RST : Enable reset TC when MR2 matches TC
bits : 7 - 14
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR2 matches TC

End of enumeration elements list.

MR2STOP : Stop TC and PC and clear CEN bit when MR2 matches TC
bits : 8 - 16
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR2 matches TC

End of enumeration elements list.

MR3IE : Enable generating an interrupt when MR3 matches TC
bits : 9 - 18
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR3 matches TC

End of enumeration elements list.

MR3RST : Enable reset TC when MR3 matches TC
bits : 10 - 20
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR3 matches TC

End of enumeration elements list.

MR3STOP : Stop TC and PC and clear CEN bit when MR3 matches TC
bits : 11 - 22
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR3 matches TC

End of enumeration elements list.

MR4IE : Enable generating an interrupt when MR4 matches TC
bits : 12 - 24
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR4 matches TC

End of enumeration elements list.

MR4RST : Enable reset TC when MR4 matches TC
bits : 13 - 26
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR4 matches TC

End of enumeration elements list.

MR4STOP : Stop TC and PC and clear CEN bit when MR4 matches TC
bits : 14 - 28
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR4 matches TC

End of enumeration elements list.

MR5IE : Enable generating an interrupt when MR5 matches TC
bits : 15 - 30
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR5 matches TC

End of enumeration elements list.

MR5RST : Enable reset TC when MR5 matches TC
bits : 16 - 32
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR5 matches TC

End of enumeration elements list.

MR5STOP : Stop TC and PC and clear CEN bit when MR5 matches TC
bits : 17 - 34
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR5 matches TC

End of enumeration elements list.

MR6IE : Enable generating an interrupt when MR6 matches TC
bits : 18 - 36
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR6 matches TC

End of enumeration elements list.

MR6RST : Enable reset TC when MR6 matches TC
bits : 19 - 38
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR6 matches TC

End of enumeration elements list.

MR6STOP : Stop TC and PC and clear CEN bit when MR6 matches TC
bits : 20 - 40
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR6 matches TC

End of enumeration elements list.

MR7IE : Enable generating an interrupt when MR7 matches TC
bits : 21 - 42
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR7 matches TC

End of enumeration elements list.

MR7RST : Enable reset TC when MR7 matches TC
bits : 22 - 44
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR7 matches TC

End of enumeration elements list.

MR7STOP : Stop TC and PC and clear CEN bit when MR7 matches TC
bits : 23 - 46
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR7 matches TC

End of enumeration elements list.

MR8IE : Enable generating an interrupt when MR8 matches TC
bits : 24 - 48
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR8 matches TC

End of enumeration elements list.

MR8RST : Enable reset TC when MR8 matches TC
bits : 25 - 50
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR8 matches TC

End of enumeration elements list.

MR8STOP : Stop TC and PC and clear CEN bit when MR8 matches TC
bits : 26 - 52
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR8 matches TC

End of enumeration elements list.

MR9IE : Enable generating an interrupt when MR9 matches TC
bits : 27 - 54
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR9 matches TC

End of enumeration elements list.

MR9RST : Enable reset TC when MR9 matches TC
bits : 28 - 56
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR9 matches TC

End of enumeration elements list.

MR9STOP : Stop TC and PC and clear CEN bit when MR9 matches TC
bits : 29 - 58
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR9 matches TC

End of enumeration elements list.


MCTRL2

Offset:0x18 CT16Bn Match Control Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR10IE MR10RST MR10STOP MR11IE MR11RST MR11STOP MR12IE MR12RST MR12STOP

MR10IE : Enable generating an interrupt when MR10 matches TC
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR10 matches TC

End of enumeration elements list.

MR10RST : Enable reset TC when MR10 matches TC
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR10 matches TC

End of enumeration elements list.

MR10STOP : Stop TC and PC and clear CEN bit when MR10 matches TC
bits : 2 - 4
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR10 matches TC

End of enumeration elements list.

MR11IE : Enable generating an interrupt when MR11 matches TC
bits : 3 - 6
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR11 matches TC

End of enumeration elements list.

MR11RST : Enable reset TC when MR11 matches TC
bits : 4 - 8
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR11 matches TC

End of enumeration elements list.

MR11STOP : Stop TC and PC and clear CEN bit when MR11 matches TC
bits : 5 - 10
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR11 matches TC

End of enumeration elements list.

MR12IE : Enable generating an interrupt when MR12 matches TC
bits : 6 - 12
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR12 matches TC

End of enumeration elements list.

MR12RST : Enable reset TC when MR12 matches TC
bits : 7 - 14
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR12 matches TC

End of enumeration elements list.

MR12STOP : Stop TC and PC and clear CEN bit when MR12 matches TC
bits : 8 - 16
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR12 matches TC

End of enumeration elements list.


MR0

Offset:0x20 CT16Bn MR0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR1

Offset:0x24 CT16Bn MR1 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR2

Offset:0x28 CT16Bn MR2 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR3

Offset:0x2C CT16Bn MR3 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR4

Offset:0x30 CT16Bn MR4 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR5

Offset:0x34 CT16Bn MR5 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR6

Offset:0x38 CT16Bn MR6 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR7

Offset:0x3C CT16Bn MR7 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TC

Offset:0x04 CT16Bn Timer Counter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC

TC : Timer Counter
bits : 0 - 15
access : read-write


MR8

Offset:0x40 CT16Bn MR8 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR9

Offset:0x44 CT16Bn MR9 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR10

Offset:0x48 CT16Bn MR10 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR11

Offset:0x4C CT16Bn MR11 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR12

Offset:0x50 CT16Bn MR12 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRE

Offset:0x08 CT16Bn Prescale Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRE

PRE : Prescaler
bits : 0 - 7
access : read-write


CAPCTRL

Offset:0x84 CT16Bn Capture Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0RE CAP0FE CAP0IE CAP0EN

CAP0RE : Capture/Reset on CT16Bn_CAP0 signal rising edge
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.

End of enumeration elements list.

CAP0FE : Capture/Reset on CT16Bn_CAP0 signal falling edge
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.

End of enumeration elements list.

CAP0IE : Interrupt on CT16Bn_CAP0 event
bits : 2 - 4
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.

End of enumeration elements list.

CAP0EN : CAP0 function enable
bits : 3 - 6
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Enable CAP0 function for external Capture pin

End of enumeration elements list.


CAP0

Offset:0x88 CT16Bn CAP0 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0

CAP0 : Timer counter capture value
bits : 0 - 15
access : read-only


EM

Offset:0x8C CT16Bn External Match Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM0 EM1 EM2 EM3 EM4 EM5 EM6 EM7 EM8 EM9 EM10 EM11

EM0 : When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
bits : 0 - 0
access : read-write

EM1 : When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
bits : 1 - 2
access : read-write

EM2 : When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output.
bits : 2 - 4
access : read-write

EM3 : When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output.
bits : 3 - 6
access : read-write

EM4 : When the TC matches MR4, this bit will act according to EMC4[1:0], and also drive the state of CT16Bn_PWM0 output.
bits : 4 - 8
access : read-write

EM5 : When the TC matches MR5, this bit will act according to EMC5[1:0], and also drive the state of CT16Bn_PWM1 output.
bits : 5 - 10
access : read-write

EM6 : When the TC matches MR6, this bit will act according to EMC6[1:0], and also drive the state of CT16Bn_PWM2 output.
bits : 6 - 12
access : read-write

EM7 : When the TC matches MR7, this bit will act according to EMC7[1:0], and also drive the state of CT16Bn_PWM3 output.
bits : 7 - 14
access : read-write

EM8 : When the TC matches MR8, this bit will act according to EMC8[1:0], and also drive the state of CT16Bn_PWM0 output.
bits : 8 - 16
access : read-write

EM9 : When the TC matches MR9, this bit will act according to EMC9[1:0], and also drive the state of CT16Bn_PWM1 output.
bits : 9 - 18
access : read-write

EM10 : When the TC matches MR10, this bit will act according to EMC10[1:0], and also drive the state of CT16Bn_PWM2 output.
bits : 10 - 20
access : read-write

EM11 : When the TC matches MR11, this bit will act according to EMC11[1:0], and also drive the state of CT16Bn_PWM3 output.
bits : 11 - 22
access : read-write


EMC

Offset:0x90 CT16Bn External Match Control register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMC0 EMC1 EMC2 EMC3 EMC4 EMC5 EMC6 EMC7 EMC8
Warning: Undefined array key 34 in /app/public/svg.inc on line 285
EMC9
Warning: Undefined array key 38 in /app/public/svg.inc on line 285
EMC10
Warning: Undefined array key 42 in /app/public/svg.inc on line 285
EMC11
Warning: Undefined array key 46 in /app/public/svg.inc on line 285

EMC0 : CT16Bn_PWM0 functionality
bits : 0 - 1
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM0 pin is LOW

2 : High

CT16Bn_PWM0 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM0 pin

End of enumeration elements list.

EMC1 : CT16Bn_PWM1 functionality
bits : 2 - 5
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM1 pin is LOW

2 : High

CT16Bn_PWM1 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM1 pin

End of enumeration elements list.

EMC2 : CT16Bn_PWM2 functionality
bits : 4 - 9
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM2 pin is LOW

2 : High

CT16Bn_PWM2 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM2 pin

End of enumeration elements list.

EMC3 : CT16Bn_PWM3 functionality
bits : 6 - 13
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM3 pin is LOW

2 : High

CT16Bn_PWM3 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM3 pin

End of enumeration elements list.

EMC4 : CT16Bn_PWM4 functionality
bits : 8 - 17
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM4 pin is LOW

2 : High

CT16Bn_PWM4 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM4 pin

End of enumeration elements list.

EMC5 : CT16Bn_PWM5 functionality
bits : 10 - 21
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM5 pin is LOW

2 : High

CT16Bn_PWM5 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM5 pin

End of enumeration elements list.

EMC6 : CT16Bn_PWM6 functionality
bits : 12 - 25
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM6 pin is LOW

2 : High

CT16Bn_PWM6 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM6 pin

End of enumeration elements list.

EMC7 : CT16Bn_PWM7 functionality
bits : 14 - 29
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM7 pin is LOW

2 : High

CT16Bn_PWM7 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM7 pin

End of enumeration elements list.

EMC8 : CT16Bn_PWM8 functionality
bits : 16 - 33
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM8 pin is LOW

2 : High

CT16Bn_PWM8 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM8 pin

End of enumeration elements list.

EMC9 : CT16Bn_PWM9 functionality
bits : 18 - 37
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM9 pin is LOW

2 : High

CT16Bn_PWM9 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM9 pin

End of enumeration elements list.

EMC10 : CT16Bn_PWM10 functionality
bits : 20 - 41
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM10 pin is LOW

2 : High

CT16Bn_PWM10 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM10 pin

End of enumeration elements list.

EMC11 : CT16Bn_PWM11 functionality
bits : 22 - 45
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM11 pin is LOW

2 : High

CT16Bn_PWM11 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM11 pin

End of enumeration elements list.


PWMCTRL

Offset:0x98 CT16Bn PWM Control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0MODE PWM1MODE PWM2MODE PWM3MODE PWM4MODE PWM5MODE PWM6MODE PWM7MODE PWM8MODE
Warning: Undefined array key 34 in /app/public/svg.inc on line 285
PWM9MODE
Warning: Undefined array key 38 in /app/public/svg.inc on line 285
PWM10MODE
Warning: Undefined array key 42 in /app/public/svg.inc on line 285
PWM11MODE
Warning: Undefined array key 46 in /app/public/svg.inc on line 285

PWM0MODE : PWM0 output mode
bits : 0 - 1
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM0 is 0 when TC is less than MR0. During down-counting, PWM0 is 1 when TC is larger/equal than MR0

1 : PWM mode 2

During up-counting, PWM0 is 1 when TC is less than MR0. During down-counting, PWM0 is 0 when TC is larger/equal than MR0

2 : Force 0

PWM0 is forced to 0

3 : Force 1

PWM0 is forced to 1

End of enumeration elements list.

PWM1MODE : PWM1 output mode
bits : 2 - 5
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM1 is 0 when TC is less than MR1. During down-counting, PWM1 is 1 when TC is larger/equal than MR1

1 : PWM mode 2

During up-counting, PWM1 is 1 when TC is less than MR1. During down-counting, PWM1 is 0 when TC is larger/equal than MR1

2 : Force 0

PWM1 is forced to 0

3 : Force 1

PWM1 is forced to 1

End of enumeration elements list.

PWM2MODE : PWM2 output mode
bits : 4 - 9
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM2 is 0 when TC is less than MR2. During down-counting, PWM2 is 1 when TC is larger/equal than MR2

1 : PWM mode 2

During up-counting, PWM2 is 1 when TC is less than MR2. During down-counting, PWM2 is 0 when TC is larger/equal than MR2

2 : Force 0

PWM2 is forced to 0

3 : Force 1

PWM2 is forced to 1

End of enumeration elements list.

PWM3MODE : PWM3 output mode
bits : 6 - 13
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM3 is 0 when TC is less than MR3. During down-counting, PWM3 is 1 when TC is larger/equal than MR3

1 : PWM mode 2

During up-counting, PWM3 is 1 when TC is less than MR3. During down-counting, PWM3 is 0 when TC is larger/equal than MR3

2 : Force 0

PWM3 is forced to 0

3 : Force 1

PWM3 is forced to 1

End of enumeration elements list.

PWM4MODE : PWM4 output mode
bits : 8 - 17
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM4 is 0 when TC is less than MR4. During down-counting, PWM4 is 1 when TC is larger/equal than MR4

1 : PWM mode 2

During up-counting, PWM4 is 1 when TC is less than MR4. During down-counting, PWM4 is 0 when TC is larger/equal than MR4

2 : Force 0

PWM4 is forced to 0

3 : Force 1

PWM4 is forced to 1

End of enumeration elements list.

PWM5MODE : PWM5 output mode
bits : 10 - 21
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM5 is 0 when TC is less than MR5. During down-counting, PWM5 is 1 when TC is larger/equal than MR5

1 : PWM mode 2

During up-counting, PWM5 is 1 when TC is less than MR5. During down-counting, PWM5 is 0 when TC is larger/equal than MR5

2 : Force 0

PWM5 is forced to 0

3 : Force 1

PWM5 is forced to 1

End of enumeration elements list.

PWM6MODE : PWM6 output mode
bits : 12 - 25
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM6 is 0 when TC is less than MR6. During down-counting, PWM6 is 1 when TC is larger/equal than MR6

1 : PWM mode 2

During up-counting, PWM6 is 1 when TC is less than MR6. During down-counting, PWM6 is 0 when TC is larger/equal than MR6

2 : Force 0

PWM6 is forced to 0

3 : Force 1

PWM6 is forced to 1

End of enumeration elements list.

PWM7MODE : PWM7 output mode
bits : 14 - 29
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM7 is 0 when TC is less than MR7. During down-counting, PWM7 is 1 when TC is larger/equal than MR7

1 : PWM mode 2

During up-counting, PWM7 is 1 when TC is less than MR7. During down-counting, PWM7 is 0 when TC is larger/equal than MR7

2 : Force 0

PWM7 is forced to 0

3 : Force 1

PWM7 is forced to 1

End of enumeration elements list.

PWM8MODE : PWM8 output mode
bits : 16 - 33
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM8 is 0 when TC is less than MR8. During down-counting, PWM8 is 1 when TC is larger/equal than MR8

1 : PWM mode 2

During up-counting, PWM8 is 1 when TC is less than MR8. During down-counting, PWM8 is 0 when TC is larger/equal than MR8

2 : Force 0

PWM8 is forced to 0

3 : Force 1

PWM8 is forced to 1

End of enumeration elements list.

PWM9MODE : PWM9 output mode
bits : 18 - 37
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM9 is 0 when TC is less than MR9. During down-counting, PWM9 is 1 when TC is larger/equal than MR9

1 : PWM mode 2

During up-counting, PWM9 is 1 when TC is less than MR9. During down-counting, PWM9 is 0 when TC is larger/equal than MR9

2 : Force 0

PWM9 is forced to 0

3 : Force 1

PWM9 is forced to 1

End of enumeration elements list.

PWM10MODE : PWM10 output mode
bits : 20 - 41
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM10 is 0 when TC is less than MR10. During down-counting, PWM10 is 1 when TC is larger/equal than MR10

1 : PWM mode 2

During up-counting, PWM10 is 1 when TC is less than MR10. During down-counting, PWM10 is 0 when TC is larger/equal than MR10

2 : Force 0

PWM10 is forced to 0

3 : Force 1

PWM10 is forced to 1

End of enumeration elements list.

PWM11MODE : PWM11 output mode
bits : 22 - 45
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM11 is 0 when TC is less than MR11. During down-counting, PWM11 is 1 when TC is larger/equal than MR11

1 : PWM mode 2

During up-counting, PWM11 is 1 when TC is less than MR11. During down-counting, PWM11 is 0 when TC is larger/equal than MR11

2 : Force 0

PWM11 is forced to 0

3 : Force 1

PWM11 is forced to 1

End of enumeration elements list.


PWMENB

Offset:0xA0 CT16Bn PWM Enable register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0EN PWM1EN PWM2EN PWM3EN PWM4EN PWM5EN PWM6EN PWM7EN PWM8EN PWM9EN PWM10EN PWM11EN

PWM0EN : PWM0 enable
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM0 is controlled by EM0

1 : Enable

Enable PWM mode for CT16Bn_PWM0

End of enumeration elements list.

PWM1EN : PWM1 enable
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM1 is controlled by EM1

1 : Enable

Enable PWM mode for CT16Bn_PWM1

End of enumeration elements list.

PWM2EN : PWM2 enable
bits : 2 - 4
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM2 is controlled by EM2

1 : Enable

Enable PWM mode for CT16Bn_PWM2

End of enumeration elements list.

PWM3EN : PWM3 enable
bits : 3 - 6
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM3 is controlled by EM3

1 : Enable

Enable PWM mode for CT16Bn_PWM3

End of enumeration elements list.

PWM4EN : PWM4 enable
bits : 4 - 8
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM4 is controlled by EM4

1 : Enable

Enable PWM mode for CT16Bn_PWM4

End of enumeration elements list.

PWM5EN : PWM5 enable
bits : 5 - 10
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM5 is controlled by EM5

1 : Enable

Enable PWM mode for CT16Bn_PWM5

End of enumeration elements list.

PWM6EN : PWM6 enable
bits : 6 - 12
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM6 is controlled by EM6

1 : Enable

Enable PWM mode for CT16Bn_PWM6

End of enumeration elements list.

PWM7EN : PWM7 enable
bits : 7 - 14
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM7 is controlled by EM7

1 : Enable

Enable PWM mode for CT16Bn_PWM7

End of enumeration elements list.

PWM8EN : PWM8 enable
bits : 8 - 16
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM8 is controlled by EM8

1 : Enable

Enable PWM mode for CT16Bn_PWM8

End of enumeration elements list.

PWM9EN : PWM9 enable
bits : 9 - 18
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM9 is controlled by EM9

1 : Enable

Enable PWM mode for CT16Bn_PWM9

End of enumeration elements list.

PWM10EN : PWM10 enable
bits : 10 - 20
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM10 is controlled by EM10

1 : Enable

Enable PWM mode for CT16Bn_PWM10

End of enumeration elements list.

PWM11EN : PWM11 enable
bits : 11 - 22
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM11 is controlled by EM11

1 : Enable

Enable PWM mode for CT16Bn_PWM11

End of enumeration elements list.


PWMIOENB

Offset:0xA4 CT16Bn PWM IO Enable register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0IOEN PWM1IOEN PWM2IOEN PWM3IOEN PWM4IOEN PWM5IOEN PWM6IOEN PWM7IOEN PWM8IOEN PWM9IOEN PWM10IOEN PWM11IOEN

PWM0IOEN : CT16Bn_PWM0/GPIO selection
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM0 pin is act as GPIO

1 : Enable

CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit

End of enumeration elements list.

PWM1IOEN : CT16Bn_PWM1/GPIO selection
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM1 pin is act as GPIO

1 : Enable

CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit

End of enumeration elements list.

PWM2IOEN : CT16Bn_PWM2/GPIO selection
bits : 2 - 4
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM2 pin is act as GPIO

1 : Enable

CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit

End of enumeration elements list.

PWM3IOEN : CT16Bn_PWM3/GPIO selection
bits : 3 - 6
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM3 pin is act as GPIO

1 : Enable

CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit

End of enumeration elements list.

PWM4IOEN : CT16Bn_PWM4/GPIO selection
bits : 4 - 8
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM4 pin is act as GPIO

1 : Enable

CT16Bn_PWM4 pin act as match output, and output depends on PWM4EN bit

End of enumeration elements list.

PWM5IOEN : CT16Bn_PWM5/GPIO selection
bits : 5 - 10
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM5 pin is act as GPIO

1 : Enable

CT16Bn_PWM5 pin act as match output, and output depends on PWM5EN bit

End of enumeration elements list.

PWM6IOEN : CT16Bn_PWM6/GPIO selection
bits : 6 - 12
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM6 pin is act as GPIO

1 : Enable

CT16Bn_PWM6 pin act as match output, and output depends on PWM6EN bit

End of enumeration elements list.

PWM7IOEN : CT16Bn_PWM7/GPIO selection
bits : 7 - 14
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM7 pin is act as GPIO

1 : Enable

CT16Bn_PWM7 pin act as match output, and output depends on PWM7EN bit

End of enumeration elements list.

PWM8IOEN : CT16Bn_PWM8/GPIO selection
bits : 8 - 16
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM8 pin is act as GPIO

1 : Enable

CT16Bn_PWM8 pin act as match output, and output depends on PWM8EN bit

End of enumeration elements list.

PWM9IOEN : CT16Bn_PWM9/GPIO selection
bits : 9 - 18
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM9 pin is act as GPIO

1 : Enable

CT16Bn_PWM9 pin act as match output, and output depends on PWM9EN bit

End of enumeration elements list.

PWM10IOEN : CT16Bn_PWM10/GPIO selection
bits : 10 - 20
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM10 pin is act as GPIO

1 : Enable

CT16Bn_PWM10 pin act as match output, and output depends on PWM10EN bit

End of enumeration elements list.

PWM11IOEN : CT16Bn_PWM11/GPIO selection
bits : 11 - 22
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM11 pin is act as GPIO

1 : Enable

CT16Bn_PWM11 pin act as match output, and output depends on PWM11EN bit

End of enumeration elements list.


RIS

Offset:0xA8 CT16Bn Raw Interrupt Status Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IF MR1IF MR2IF MR3IF MR4IF MR5IF MR6IF MR7IF MR8IF MR9IF MR10IF MR11IF MR12IF CAP0IF

MR0IF : Match channel 0 interrupt flag
bits : 0 - 0
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 0

1 : Met interrupt requirements

Interrupt requirements met on match channel 0

End of enumeration elements list.

MR1IF : Match channel 1 interrupt flag
bits : 1 - 2
access : read-only

Enumeration:

0 : No

No interrupt on match channel 1

1 : Met interrupt requirements

Interrupt requirements met on match channel 1

End of enumeration elements list.

MR2IF : Match channel 2 interrupt flag
bits : 2 - 4
access : read-only

Enumeration:

0 : No

No interrupt on match channel 2

1 : Met interrupt requirements

Interrupt requirements met on match channel 2

End of enumeration elements list.

MR3IF : Match channel 3 interrupt flag
bits : 3 - 6
access : read-only

Enumeration:

0 : No

No interrupt on match channel 3

1 : Met interrupt requirements

Interrupt requirements met on match channel 3

End of enumeration elements list.

MR4IF : Match channel 4 interrupt flag
bits : 4 - 8
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 4

1 : Met interrupt requirements

Interrupt requirements met on match channel 4

End of enumeration elements list.

MR5IF : Match channel 5 interrupt flag
bits : 5 - 10
access : read-only

Enumeration:

0 : No

No interrupt on match channel 5

1 : Met interrupt requirements

Interrupt requirements met on match channel 5

End of enumeration elements list.

MR6IF : Match channel 6 interrupt flag
bits : 6 - 12
access : read-only

Enumeration:

0 : No

No interrupt on match channel 6

1 : Met interrupt requirements

Interrupt requirements met on match channel 6

End of enumeration elements list.

MR7IF : Match channel 7 interrupt flag
bits : 7 - 14
access : read-only

Enumeration:

0 : No

No interrupt on match channel 7

1 : Met interrupt requirements

Interrupt requirements met on match channel 7

End of enumeration elements list.

MR8IF : Match channel 8 interrupt flag
bits : 8 - 16
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 8

1 : Met interrupt requirements

Interrupt requirements met on match channel 8

End of enumeration elements list.

MR9IF : Match channel 9 interrupt flag
bits : 9 - 18
access : read-only

Enumeration:

0 : No

No interrupt on match channel 9

1 : Met interrupt requirements

Interrupt requirements met on match channel 9

End of enumeration elements list.

MR10IF : Match channel 10 interrupt flag
bits : 10 - 20
access : read-only

Enumeration:

0 : No

No interrupt on match channel 10

1 : Met interrupt requirements

Interrupt requirements met on match channel 10

End of enumeration elements list.

MR11IF : Match channel 11 interrupt flag
bits : 11 - 22
access : read-only

Enumeration:

0 : No

No interrupt on match channel 11

1 : Met interrupt requirements

Interrupt requirements met on match channel 11

End of enumeration elements list.

MR12IF : Match channel 12 interrupt flag
bits : 12 - 24
access : read-only

Enumeration:

0 : No

No interrupt on match channel 12

1 : Met interrupt requirements

Interrupt requirements met on match channel 12

End of enumeration elements list.

CAP0IF : Capture channel 0 interrupt flag
bits : 13 - 26
access : read-only

Enumeration:

0 : No

No interrupt on CAP0

1 : Met interrupt requirements

Interrupt requirements met on CAP0

End of enumeration elements list.


IC

Offset:0xAC CT16Bn Interrupt Clear Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IC MR1IC MR2IC MR3IC MR4IC MR5IC MR6IC MR7IC MR8IC MR9IC MR10IC MR11IC MR12IC CAP0IC

MR0IC : MR0IF clear bit
bits : 0 - 0
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR0IF

End of enumeration elements list.

MR1IC : MR1IF clear bit
bits : 1 - 2
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR1IF

End of enumeration elements list.

MR2IC : MR2IF clear bit
bits : 2 - 4
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR2IF

End of enumeration elements list.

MR3IC : MR3IF clear bit
bits : 3 - 6
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR3IF

End of enumeration elements list.

MR4IC : MR4IF clear bit
bits : 4 - 8
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR4IF

End of enumeration elements list.

MR5IC : MR5IF clear bit
bits : 5 - 10
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR5IF

End of enumeration elements list.

MR6IC : MR6IF clear bit
bits : 6 - 12
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR6IF

End of enumeration elements list.

MR7IC : MR7IF clear bit
bits : 7 - 14
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR7IF

End of enumeration elements list.

MR8IC : MR8IF clear bit
bits : 8 - 16
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR8IF

End of enumeration elements list.

MR9IC : MR9IF clear bit
bits : 9 - 18
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR9IF

End of enumeration elements list.

MR10IC : MR10IF clear bit
bits : 10 - 20
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR10IF

End of enumeration elements list.

MR11IC : MR11IF clear bit
bits : 11 - 22
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR11IF

End of enumeration elements list.

MR12IC : MR12IF clear bit
bits : 12 - 24
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR12IF

End of enumeration elements list.

CAP0IC : CAP0IF clear bit
bits : 13 - 26
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CAP0IF

End of enumeration elements list.


PC

Offset:0x0C CT16Bn Prescale Counter Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC

PC : Prescaler Counter
bits : 0 - 7
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.