SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL0

IE

RIS

IC

DATA

DFDLY

DMACTRL

DMACNT

DMAHTCNT

CURCNT

CTRL1

CLKDIV

STAT


CTRL0

Offset:0x00 SPI0 Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIEN LOOPBACK SDODIS MS FORMAT FRESET DL TXFIFOTH RXFIFOTH
Warning: Undefined array key 33 in /app/public/svg.inc on line 285
SELDIS
Warning: Undefined array key 37 in /app/public/svg.inc on line 285

SPIEN : SPI enable
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable SPI

1 : Enable

Enable SPI

End of enumeration elements list.

LOOPBACK : Loopback mode enable
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

Disable loopback mode

1 : Enable

Enable loopback mode

End of enumeration elements list.

SDODIS : Slave data out disable
bits : 2 - 4
access : read-write

Enumeration:

0 : Enable

Enable slave data out

1 : Disble

Diable slave data out (MISO=0)

End of enumeration elements list.

MS : Master/Slave selection
bits : 3 - 6
access : read-write

Enumeration:

0 : Master

Act as Master

1 : Slave

Act as Slave

End of enumeration elements list.

FORMAT : Interface format
bits : 4 - 8
access : read-write

Enumeration:

0 : SPI

SPI format

End of enumeration elements list.

FRESET : SPI FSM and FIFO Reset
bits : 6 - 13
access : write-only

Enumeration:

0 : 00

No effect

3 : 11

Reset FSM and FIFO

End of enumeration elements list.

DL : Data length = DL[3:0]+1
bits : 8 - 19
access : read-write

Enumeration:

2 : 0010

Data length=3

3 : 0011

Data length=4

4 : 0100

Data length=5

5 : 0101

Data length=6

6 : 0110

Data length=7

7 : 0111

Data length=8

8 : 1000

Data length=9

9 : 1001

Data length=10

10 : 1010

Data length=11

11 : 1011

Data length=12

12 : 1100

Data length=13

13 : 1101

Data length=14

14 : 1110

Data length=15

15 : 1111

Data length=16

End of enumeration elements list.

TXFIFOTH : TX FIFO Threshold level
bits : 12 - 26
access : read-write

Enumeration:

0 : 0

TX FIFO threshold level is 0

1 : 1

TX FIFO threshold level is 1

2 : 2

TX FIFO threshold level is 2

3 : 3

TX FIFO threshold level is 3

4 : 4

TX FIFO threshold level is 4

5 : 5

TX FIFO threshold level is 5

6 : 6

TX FIFO threshold level is 6

7 : 7

TX FIFO threshold level is 7

End of enumeration elements list.

RXFIFOTH : RX FIFO Threshold level
bits : 15 - 32
access : read-write

Enumeration:

0 : 0

RX FIFO threshold level is 0

1 : 1

RX FIFO threshold level is 1

2 : 2

RX FIFO threshold level is 2

3 : 3

RX FIFO threshold level is 3

4 : 4

RX FIFO threshold level is 4

5 : 5

RX FIFO threshold level is 5

6 : 6

RX FIFO threshold level is 6

7 : 7

RX FIFO threshold level is 7

End of enumeration elements list.

SELDIS : Auto-SEL disable bit
bits : 18 - 36
access : read-write

Enumeration:

0 : Enable

Enable Auto-SEL flow control

1 : Disable

Disable Auto-SEL flow control

End of enumeration elements list.


IE

Offset:0x10 SPI0 Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXOVFIE RXTOIE RXFIFOTHIE TXFIFOTHIE DMAHTIE DMATCIE

RXOVFIE : RX FIFO overflow interrupt enable
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable RX FIFO overflow interrupt

1 : Enable

Enable RX FIFO overflow interrupt

End of enumeration elements list.

RXTOIE : RX time-out interrupt enable
bits : 1 - 2
access : read-write

Enumeration:

0 : Disable

Disable RX time-out interrupt

1 : Enable

Enable RX time-out interrupt

End of enumeration elements list.

RXFIFOTHIE : RX FIFO threshold interrupt enable
bits : 2 - 4
access : read-write

Enumeration:

0 : Disable

Disable RX FIFO threshold interrupt

1 : Enable

Enable RX FIFO threshold interrupt

End of enumeration elements list.

TXFIFOTHIE : TX FIFO threshold interrupt enable
bits : 3 - 6
access : read-write

Enumeration:

0 : Disable

Disable TX FIFO threshold interrupt

1 : Enable

Enable TX FIFO threshold interrupt

End of enumeration elements list.

DMAHTIE : DMA half transfer interrupt enable bit
bits : 4 - 8
access : read-write

Enumeration:

0 : Disable

Disable DMA half transfer interrupt

1 : Enable

Enable DMA half transfer interrupt

End of enumeration elements list.

DMATCIE : DMA transfer complete interrupt enable bit
bits : 5 - 10
access : read-write

Enumeration:

0 : Disable

Disable DMA transfer complete interrupt

1 : Enable

Enable DMA transfer complete interrupt

End of enumeration elements list.


RIS

Offset:0x14 SPI0 Raw Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXOVFIF RXTOIF RXFIFOTHIF TXFIFOTHIF DMAHTIF DMATCIF

RXOVFIF : RX FIFO overflow interrupt flag
bits : 0 - 0
access : read-only

Enumeration:

0 : No

No RXOVF interrupt

1 : Met

RXOVF interrupt is triggered when RXOVFIE=1

End of enumeration elements list.

RXTOIF : RX time-out interrupt flag
bits : 1 - 2
access : read-only

Enumeration:

0 : No

No RXTO interrupt

1 : Met

RXTO interrupt is triggered when RXTOIE=1

End of enumeration elements list.

RXFIFOTHIF : RX FIFO threshold interrupt flag
bits : 2 - 4
access : read-only

Enumeration:

0 : No

No RXFIFOTH interrupt

1 : Met

RX FIFO threshold is triggered when RXFIFOTHIE=1

End of enumeration elements list.

TXFIFOTHIF : TX FIFO threshold interrupt flag
bits : 3 - 6
access : read-only

Enumeration:

0 : No

No TXFIFOTH interrupt

1 : Met

TX FIFO threshold is triggered when TXFIFOTHIE=1

End of enumeration elements list.

DMAHTIF : RX FIFO threshold interrupt flag
bits : 4 - 8
access : read-only

Enumeration:

0 : No

No half transfer event

1 : Met

A half transfer event occurs

End of enumeration elements list.

DMATCIF : DMA transfer complete flag
bits : 5 - 10
access : read-only

Enumeration:

0 : No

No transfer completion

1 : Met

A transfer complete event occurs

End of enumeration elements list.


IC

Offset:0x18 SPI0 Interrupt Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXOVFIC RXTOIC RXFIFOTHIC TXFIFOTHIC DMAHTIC DMATCIC

RXOVFIC : RX FIFO overflow flag clear
bits : 0 - 0
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear RXOVF flag

End of enumeration elements list.

RXTOIC : RX time-out interrupt flag clear
bits : 1 - 2
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear RXTO flag

End of enumeration elements list.

RXFIFOTHIC : RX Interrupt flag Clear
bits : 2 - 4
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear RXFIFOTH flag

End of enumeration elements list.

TXFIFOTHIC : TX Interrupt flag Clear
bits : 3 - 6
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear TXFIFOTH flag

End of enumeration elements list.

DMAHTIC : Select the DMAHTIF flag to be cleared
bits : 4 - 8
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear DMAHTIF flag

End of enumeration elements list.

DMATCIC : Select the DMATCIF flag to be cleared
bits : 5 - 10
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear DMATCIF flag

End of enumeration elements list.


DATA

Offset:0x1C SPI0 Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data

Data : Data
bits : 0 - 15
access : read-write


DFDLY

Offset:0x20 SPI0 Data Fetch Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFETCH_EN

DFETCH_EN : SPI0 data fetch control bit
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Enable when SCKn frequency is higher than 6MHz

End of enumeration elements list.


DMACTRL

Offset:0x24 SPI0 DMA Control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN DIR

DMAEN : SPI to SPI DMA enable bit
bits : 0 - 0
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

DIR : SPI data transfer direction
bits : 1 - 2
access : read-write

Enumeration:

0 : SPI1toSPI0

SPI1_DATA(RX) to SPI0_DATA(TX), when DMATCIE and DMAHTIE enable, and trigger SPI0 interrupt

1 : SPI0toSPI1

SPI0_DATA(RX) to SPI1_DATA(TX) , when DMATCIE and DMAHTIE enable, and trigger SPI1 interrupt

End of enumeration elements list.


DMACNT

Offset:0x28 SPI0 DMA Control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Number of data to DMA RX count transfer
bits : 0 - 27
access : read-write


DMAHTCNT

Offset:0x2C SPI0 DMA Control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTCNT

HTCNT : Number of data to DMA RX half count transfer
bits : 0 - 27
access : read-write


CURCNT

Offset:0x30 SPI0 DMA Control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURCNT

CURCNT : This field indicates DMA current transfer data counter pointer.
bits : 0 - 27
access : read-only


CTRL1

Offset:0x04 SPI0 Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MLSB CPOL CPHA

MLSB : MSB/LSB seletion
bits : 0 - 0
access : read-write

Enumeration:

0 : MSB

MSB transmit first

1 : LSB

LSB transmit first

End of enumeration elements list.

CPOL : Clock priority selection
bits : 1 - 2
access : read-write

Enumeration:

0 : Low

SCK idles at low level

1 : High

SCK idles at high level

End of enumeration elements list.

CPHA : Clock phase of edge sampling
bits : 2 - 4
access : read-write

Enumeration:

0 : CPHA0

The 1st bit is fixed already, and SCK 1st edge is to receive/transmit data

1 : CPHA1

SCK 1st edge is for data transition, and receive/transmit data at 2nd edge

End of enumeration elements list.


CLKDIV

Offset:0x08 SPI0 Clock Divider Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : SPI0 SCK
bits : 0 - 7
access : read-write


STAT

Offset:0x0C SPI0 Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_EMPTY TX_FULL RX_EMPTY RX_FULL BUSY TXFIFOTHF RXFIFOTHF

TX_EMPTY : TX FIFO empty flag
bits : 0 - 0
access : read-only

Enumeration:

0 : 0

TX FIFO is not empty

1 : 1

TX FIFO is empty

End of enumeration elements list.

TX_FULL : TX FIFO full flag
bits : 1 - 2
access : read-only

Enumeration:

0 : 0

TX FIFO is not full

1 : 1

TX FIFO is full

End of enumeration elements list.

RX_EMPTY : RX FIFO empty flag
bits : 2 - 4
access : read-only

Enumeration:

0 : 0

RX FIFO is not empty

1 : 1

RX FIFO is empty

End of enumeration elements list.

RX_FULL : RX FIFO full flag
bits : 3 - 6
access : read-only

Enumeration:

0 : 0

RX FIFO is not full

1 : 1

RX FIFO is full

End of enumeration elements list.

BUSY : Busy flag
bits : 4 - 8
access : read-only

Enumeration:

0 : Idle

SSPn is idle

1 : Busy

SSPn is transfering

End of enumeration elements list.

TXFIFOTHF : TX FIFO threshold flag
bits : 5 - 10
access : read-only

Enumeration:

0 : 0

Data count in TX FIFO is larger than TXFIFOTH

1 : 1

Data count in TX FIFO is less equal than TXFIFOTH

End of enumeration elements list.

RXFIFOTHF : RX FIFO threshold flag
bits : 6 - 12
access : read-only

Enumeration:

0 : 0

Data count in RX FIFO is less equal than RXFIFOTH

1 : 1

Data count in RX FIFO is larger than RXFIFOTH

End of enumeration elements list.



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