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VC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

CR0

CR1

OUTCFG

SR


CR0

VC Control 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINSEL NINSEL V25DIV V25DIV_EN

PINSEL : No Comment
bits : 0 - 1 (2 bit)
access : read-write

NINSEL : No Comment
bits : 2 - 3 (2 bit)
access : read-write

V25DIV : No Comment
bits : 4 - 5 (2 bit)
access : read-write

V25DIV_EN : No Comment
bits : 6 - 6 (1 bit)
access : read-write


CR1

VC Control 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCEN VC_FLTCLK_SEL FLTEN FALLINTEN RISEINTEN HIGHINTEN INT_EN FLT_NUM

VCEN : No Comment
bits : 0 - 0 (1 bit)
access : read-write

VC_FLTCLK_SEL : No Comment
bits : 2 - 3 (2 bit)
access : read-write

FLTEN : No Comment
bits : 8 - 8 (1 bit)
access : read-write

FALLINTEN : No Comment
bits : 12 - 12 (1 bit)
access : read-write

RISEINTEN : No Comment
bits : 13 - 13 (1 bit)
access : read-write

HIGHINTEN : No Comment
bits : 14 - 14 (1 bit)
access : read-write

INT_EN : No Comment
bits : 15 - 15 (1 bit)
access : read-write

FLT_NUM : No Comment
bits : 16 - 31 (16 bit)
access : read-write


OUTCFG

VC Output Config
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCFG OUTCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INV_TIMX TIM0_EN TIM1_EN LPTIM_EN LPTIMEXT_EN INV_PCA PCACAP0_EN PCAECI_EN INV_TM1CH1 TM1CH1_EN INV_TM1CH2 TM1CH2_EN INV_TM1CH3 TIM1CH3_EN INV_TM1CH4 TM1CH3_EN TM1BKE INV_PAD

INV_TIMX : No Comment
bits : 0 - 0 (1 bit)
access : read-write

TIM0_EN : No Comment
bits : 1 - 1 (1 bit)
access : read-write

TIM1_EN : No Comment
bits : 2 - 2 (1 bit)
access : read-write

LPTIM_EN : No Comment
bits : 4 - 4 (1 bit)
access : read-write

LPTIMEXT_EN : No Comment
bits : 5 - 5 (1 bit)
access : read-write

INV_PCA : No Comment
bits : 6 - 6 (1 bit)
access : read-write

PCACAP0_EN : No Comment
bits : 7 - 7 (1 bit)
access : read-write

PCAECI_EN : No Comment
bits : 8 - 8 (1 bit)
access : read-write

INV_TM1CH1 : No Comment
bits : 9 - 9 (1 bit)
access : read-write

TM1CH1_EN : No Comment
bits : 10 - 10 (1 bit)
access : read-write

INV_TM1CH2 : No comment
bits : 11 - 11 (1 bit)
access : read-write

TM1CH2_EN : No comment
bits : 12 - 12 (1 bit)
access : read-write

INV_TM1CH3 : No comment
bits : 13 - 13 (1 bit)
access : read-write

TIM1CH3_EN : No comment
bits : 14 - 14 (1 bit)
access : read-write

INV_TM1CH4 : No comment
bits : 15 - 15 (1 bit)
access : read-write

TM1CH3_EN : No comment
bits : 16 - 16 (1 bit)
access : read-write

TM1BKE : No comment
bits : 17 - 17 (1 bit)
access : read-write

INV_PAD : No comment
bits : 18 - 18 (1 bit)
access : read-write


SR

VC Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTF VC_FLOUT

INTF : No comment
bits : 0 - 0 (1 bit)
access : read-write

VC_FLOUT : No comment
bits : 1 - 1 (1 bit)
access : read-only



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