\n
address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection :
ADC Config Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCEN : ADC Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
disabled
1 : 1
enabled
End of enumeration elements list.
START : Start Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
ADC Stop
1 : 1
ADC Run
End of enumeration elements list.
CLKSEL : ADC Clock Select
bits : 4 - 6 (3 bit)
access : read-write
SEL : ADC Channel Select
bits : 8 - 10 (3 bit)
access : read-write
SAM : ADC Sample Circle Select
bits : 11 - 11 (1 bit)
access : read-write
STATERST : ADC Continue Convert Status Control
bits : 15 - 15 (1 bit)
access : read-write
Channel 1 Result Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Result1 : Channel 1 Result
bits : 0 - 23 (24 bit)
access : read-only
Channel 2 Result Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Result2 : Channel 2 Result
bits : 0 - 11 (12 bit)
access : read-only
Channel 3 Result Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Result3 : ADC Channel 3 Result
bits : 0 - 11 (12 bit)
access : read-only
Channel 4 Result Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Result4 : Channel 4 Result
bits : 0 - 11 (12 bit)
access : read-only
Channel 5 Result Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Result5 : Channel 5 Result
bits : 0 - 11 (12 bit)
access : read-only
Channel 6 Result Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Result6 : Channel 6 Result
bits : 0 - 11 (12 bit)
access : read-only
Channel 7 Result Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Result7 : Channel 7 Result
bits : 0 - 11 (12 bit)
access : read-only
Channel Result Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESULT : Result
bits : 0 - 11 (12 bit)
access : read-only
Channel Result accumulate
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HT : Convect Result Compare High Therashold
bits : 0 - 11 (12 bit)
access : read-only
Compare High Threshold
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HT : ADC Convect Result Compare High threshold
bits : 0 - 11 (12 bit)
access : read-only
Compare Low Threshold
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT : Convect Result Compare Low Threshold
bits : 0 - 11 (12 bit)
access : read-only
ADC Config Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGS0 : ADC Convect Auto Triger 0
bits : 0 - 4 (5 bit)
access : read-write
TRIGS1 : ADC Convect Auto Triger 1
bits : 5 - 9 (5 bit)
access : read-write
CT : Convect mode Select
bits : 10 - 10 (1 bit)
access : read-write
RACC_EN : Convect Result Auto ADD
bits : 11 - 11 (1 bit)
access : read-write
LTCMP : Low threshold Compare Control
bits : 12 - 12 (1 bit)
access : read-write
HTCMP : High threshold Compare Control
bits : 13 - 13 (1 bit)
access : read-write
REGCMP : Area Compare Control
bits : 14 - 14 (1 bit)
access : read-write
RACC_CLR : Convect Result register Clear
bits : 15 - 15 (1 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCXIEN : ADC Channel 7~0 Interrupt Mask Config
bits : 0 - 7 (8 bit)
access : read-only
LLT_IEN : ADC Convect Result
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : 0
disable
1 : 1
enable
End of enumeration elements list.
HHT_IEN : HHT
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : 0
Disable
1 : 1
Enable
End of enumeration elements list.
REG_IEN : ADC
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : 0
Disable
1 : 1
Enable
End of enumeration elements list.
CONT_IEN : ADC
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : 0
Disable
1 : 1
Enable
End of enumeration elements list.
Interrupt Clear Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCICLR : Reload value to use for 10ms timing
bits : 0 - 7 (8 bit)
access : read-only
LLT_INTC : Clock Skew
bits : 8 - 8 (1 bit)
access : read-only
HHT_INTC : No Ref
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : 0
Ref Clk available
1 : 1
Ref Clk not available
End of enumeration elements list.
REG_INTC : No Ref
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : 0
Ref Clk available
1 : 1
Ref Clk not available
End of enumeration elements list.
CONT_INTC : No Ref
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : 0
Ref Clk available
1 : 1
Ref Clk not available
End of enumeration elements list.
Interrupt Status Register before mask
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCRIS : Reload value to use for 10ms timing
bits : 0 - 7 (8 bit)
access : read-only
LLT_INTF : LLT
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : 0
No comment
1 : 1
No comment
End of enumeration elements list.
HHT_INTF : HHT
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : 0
Ref Clk available
1 : 1
Ref Clk not available
End of enumeration elements list.
REG_INTF : REG
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : 0
Ref Clk available
1 : 1
Ref Clk not available
End of enumeration elements list.
CONT_INTF : CON
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : 0
Ref Clk available
1 : 1
Ref Clk not available
End of enumeration elements list.
Interrupt Status Register Behind mask
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMIS : Reload value to use for 10ms timing
bits : 0 - 7 (8 bit)
access : read-only
LLT_MIF : Clock Skew
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : 0
10ms calibration value is exact
1 : 1
10ms calibration value is inexact, because of the clock frequency
End of enumeration elements list.
HHT_MIF : No Ref
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : 0
No comment
1 : 1
No comment
End of enumeration elements list.
REG_MIF : No Ref
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : 0
Ref Clk available
1 : 1
Ref Clk not available
End of enumeration elements list.
CONT_MIF : No Ref
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : 0
Ref Clk available
1 : 1
Ref Clk not available
End of enumeration elements list.
ADC Config Register2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 7 (8 bit)
access : read-write
ADCCN : ADC Continue Convect Times Config
bits : 8 - 15 (8 bit)
access : read-write
Circle_Mode : ADC Convect Rounte Mode Select
bits : 16 - 16 (1 bit)
access : read-write
Channel 0 Result Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Result0 : ADC Channel 0 Result
bits : 0 - 11 (12 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.