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CLKTRIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

CR

IFR

ICLR

CALCON

REFCON

REFCNT

CALCNT


CR

Config Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM_START REFCLK_SEL CALCLK_SEL MON_EN IE CLKEN

TRIM_START : ADC Enable
bits : 0 - 0 (1 bit)
access : read-write

REFCLK_SEL : ADC_ Start Control
bits : 1 - 3 (3 bit)
access : read-write

CALCLK_SEL : ADC Clock Select
bits : 4 - 5 (2 bit)
access : read-write

MON_EN : ADC Channel Select
bits : 6 - 6 (1 bit)
access : read-write

IE : ADC Sample Circle Select
bits : 7 - 7 (1 bit)
access : read-write

CLKEN : ADC Continue Convert Status Control
bits : 8 - 8 (1 bit)
access : read-write


IFR

Interrupt Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFR IFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP CALCNT_OVF LXT_FAULT HXT_FAULT

STOP : ADC Channel 0 Result
bits : 0 - 0 (1 bit)
access : read-only

CALCNT_OVF : ADC Channel 0 Result
bits : 1 - 1 (1 bit)
access : read-only

LXT_FAULT : ADC Channel 0 Result
bits : 2 - 2 (1 bit)
access : read-only

HXT_FAULT : ADC Channel 0 Result
bits : 3 - 3 (1 bit)
access : read-only


ICLR

Interrupt Flag Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICLR ICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXT_FAULT_CLR HXT_FAULT_CLR

LXT_FAULT_CLR : ADC_Channel 1 Result
bits : 2 - 2 (1 bit)
access : write-only

HXT_FAULT_CLR : ADC_Channel 1 Result
bits : 3 - 3 (1 bit)
access : write-only


CALCON

Count Overtime Config Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALCON CALCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALOVCNT

CALOVCNT : ADC_Channel 2 Result
bits : 0 - 15 (16 bit)
access : read-write


REFCON

Reference Count Orignal Config Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFCON REFCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCNTVAL

RCNTVAL : ADC Convect Auto Triger 0
bits : 0 - 31 (32 bit)
access : read-write


REFCNT

Reference Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFCNT REFCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFCNT

REFCNT : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 31 (32 bit)
access : read-only


CALCNT

CAL
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALCNT CALCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALCNT

CALCNT : ADC_Channel 5 Result
bits : 0 - 31 (32 bit)
access : read-only



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