\n

OWIRE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :

Registers

CR

BITRATECNT

DRVCNT

RDSMPCNT

RECCNT

DATA

CMD

INTEN

SR

INTCLR

NFCR

RSTCNT

PRESCNT


CR

1-Wire Model Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV SIZE EN MSBFIRST RDMODE

CLKDIV : ADC Enable
bits : 0 - 1 (2 bit)
access : read-write

SIZE : ADC_ Start Control
bits : 4 - 4 (1 bit)
access : read-write

EN : ADC Clock Select
bits : 5 - 5 (1 bit)
access : read-write

MSBFIRST : ADC Channel Select
bits : 6 - 6 (1 bit)
access : read-write

RDMODE : ADC Sample Circle Select
bits : 7 - 7 (1 bit)
access : read-write


BITRATECNT

1-Wire Bit Rate Design Count
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BITRATECNT BITRATECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITRATECNT

BITRATECNT : ADC_Channel 1 Result
bits : 0 - 11 (12 bit)
access : read-write


DRVCNT

1-Wire Main Read/Write Pull0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRVCNT DRVCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRVCNT

DRVCNT : ADC_Channel 2 Result
bits : 0 - 8 (9 bit)
access : read-write


RDSMPCNT

1-Wire Main Read Sample Time Setting
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDSMPCNT RDSMPCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDSMPCNT

RDSMPCNT : ADC_Channel 5 Result
bits : 0 - 8 (9 bit)
access : read-write


RECCNT

1-Wire Recover Time Count
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RECCNT RECCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RECCNT

RECCNT : ADC_Channel 6 Result
bits : 0 - 10 (11 bit)
access : read-write


DATA

1_Wire Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRVCNT

DRVCNT : ADC Channel 3 Result
bits : 0 - 7 (8 bit)
access : read-write


CMD

1_Wire Bus Operate Command Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : ADC_Channel 4 Result
bits : 0 - 1 (2 bit)
access : read-write


INTEN

1-Wire Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKERREN INITEN TXDONEEN RXDONEEN

ACKERREN : ADC_Channel 7 Result
bits : 0 - 0 (1 bit)
access : read-write

INITEN : ADC_Channel 7 Result
bits : 1 - 1 (1 bit)
access : read-write

TXDONEEN : ADC_Channel 7 Result
bits : 2 - 2 (1 bit)
access : read-write

RXDONEEN : ADC_Channel 7 Result
bits : 3 - 3 (1 bit)
access : read-write


SR

1-Wire Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKERR INITDONE TXDONE RXDONE

ACKERR : ADC_ Result
bits : 0 - 0 (1 bit)
access : read-only

INITDONE : ADC_ Result
bits : 1 - 1 (1 bit)
access : read-only

TXDONE : ADC_ Result
bits : 2 - 2 (1 bit)
access : read-only

RXDONE : ADC_ Result
bits : 3 - 3 (1 bit)
access : read-only


INTCLR

1-Wire Interrupt Status Clean Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKERRCLR INTDONCECLR TXDONECLR RXDONECLR

ACKERRCLR : ADC_Convect Result Compare High Therashold
bits : 0 - 0 (1 bit)
access : write-only

INTDONCECLR : ADC_Convect Result Compare High Therashold
bits : 1 - 1 (1 bit)
access : write-only

TXDONECLR : ADC_Convect Result Compare High Therashold
bits : 2 - 2 (1 bit)
access : write-only

RXDONECLR : ADC_Convect Result Compare High Therashold
bits : 3 - 3 (1 bit)
access : write-only


NFCR

1-Wire Input EndPoint Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NFCR NFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFDIV NFEN

NFDIV : ADC Convect Auto Triger 0
bits : 0 - 1 (2 bit)
access : read-write

NFEN : ADC Convect Auto Triger 1
bits : 4 - 4 (1 bit)
access : read-write


RSTCNT

1-Wire Master Reset Pulse Count register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCNT RSTCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTCNT

RSTCNT : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 15 (16 bit)
access : read-write


PRESCNT

1-Wire Device Presence Pulse Count Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESCNT PRESCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCNT

PRESCNT : ADC Channel 0 Result
bits : 0 - 12 (13 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.