\n

UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

SCON

INTSR

INTCLR

BAUDCR

IRDACR

SBUF

SADDR

SADEN


SCON

UART1 Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCON SCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIEN TIEN RB8 TB8 REN SM2 SM0_SM1 DBAUD

RIEN : Receive Interrupt
bits : 0 - 0 (1 bit)
access : read-write

TIEN : Transmit Interrupt
bits : 1 - 1 (1 bit)
access : read-write

RB8 : Multi-communication bit
bits : 2 - 2 (1 bit)
access : read-write

TB8 : Multi-communication bit
bits : 3 - 3 (1 bit)
access : read-write

REN : Transmit and Receive Enable
bits : 4 - 4 (1 bit)
access : read-write

SM2 : UART multi-communication
bits : 5 - 5 (1 bit)
access : read-write

SM0_SM1 : UART mode control
bits : 6 - 7 (2 bit)
access : read-write

DBAUD : Baudrate double
bits : 9 - 9 (1 bit)
access : read-write


INTSR

Interrupt flag Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSR INTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RI TI FE

RI : Reload value to use for 10ms timing
bits : 0 - 0 (1 bit)
access : read-only

TI : Clock Skew
bits : 1 - 1 (1 bit)
access : read-only

FE : No Ref
bits : 2 - 2 (1 bit)
access : read-only


INTCLR

UART0 Interruput flag Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RICLR TICLR FECLR

RICLR : Reload value to use for 10ms timing
bits : 0 - 0 (1 bit)
access : write-only

TICLR : Clock Skew
bits : 1 - 1 (1 bit)
access : write-only

FECLR : No Ref
bits : 2 - 2 (1 bit)
access : write-only


BAUDCR

Baud Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BAUDCR BAUDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRG SELF_BRG NOREF

BRG : Reload value to use for 10ms timing
bits : 0 - 15 (16 bit)
access : read-only

SELF_BRG : Clock Skew
bits : 16 - 16 (1 bit)
access : read-only

NOREF : No Ref
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : 0

Ref Clk available

1 : 1

Ref Clk not available

End of enumeration elements list.


IRDACR

UART0 IrDA Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRDACR IRDACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC IREN IRTXINV IRRXINV IRLPMODE

PSC : Reload value to use for 10ms timing
bits : 0 - 7 (8 bit)
access : read-write

IREN : Clock Skew
bits : 8 - 8 (1 bit)
access : read-only

IRTXINV : No Ref
bits : 9 - 9 (1 bit)
access : read-write

IRRXINV : No Ref
bits : 10 - 10 (1 bit)
access : read-write

IRLPMODE : No Ref
bits : 11 - 11 (1 bit)
access : read-write


SBUF

Data BUFF
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBUF SBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBUF

SBUF : Baudrate gennerate register
bits : 0 - 7 (8 bit)
access : read-write


SADDR

Address Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDR SADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADDR

SADDR : Current value
bits : 0 - 7 (8 bit)
access : read-write


SADEN

Address Mask Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADEN SADEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADEN

SADEN : Reload value to use for 10ms timing
bits : 0 - 7 (8 bit)
access : read-only



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