\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
Count ReLoad Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RLOAD : ADC Enable
bits : 0 - 7 (8 bit)
access : read-write
WWDG Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTCLR : ADC Channel 3 Result
bits : 0 - 0 (1 bit)
access : write-only
Count Value
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDGCNT : ADC Channel 0 Result
bits : 0 - 7 (8 bit)
access : read-only
IWDG Config Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINCMP : ADC Convect Auto Triger 0
bits : 0 - 7 (8 bit)
access : read-write
PRSC : ADC Convect Auto Triger 1
bits : 8 - 27 (20 bit)
access : read-write
WWDGEN : ADC_Convect mode Select
bits : 28 - 28 (1 bit)
access : read-write
Count ReLoad Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDGIEN : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 0 (1 bit)
access : read-write
WWDG Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDGIF : ADC_Channel 1 Result
bits : 0 - 0 (1 bit)
access : read-only
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